CMOS image sensor using shared transistors between pixels having mirror symmetry

Abstract

A CMOS image sensor that has reduced transistor count is disclosed. The individual pixels are formed by a photodiode and a transfer transistor. An output node receives the signal from the photodiode via the transfer transistor. The output node is shared between multiple pixels. Further, a reset transistor is coupled between a selectable low voltage rail V ss or a high voltage reference V ref and the output node. The gate of an output transistor is then coupled to the output node. Both the reset transistor and output transistors are shared between multiple pixels. Further, the pixels have a mirror symmetry about the output transistor or output node.

1 . An apparatus comprising: 
 a first pair of pixels formed in a semiconductor substrate and using a common column readout line, each of said pixels comprising:    (1) a light sensing element; and    (2) a transfer transistor that selectively allows the transfer of signal from said light sensing element to a first floating node (FD 1 );    a second pair of pixels formed in the semiconductor substrate and using the common column readout line, each of said pixels comprising:    (1) a light sensing element; and    (2) a transfer transistor that selectively allows the transfer of signal from said light sensing element to a second floating node (FD 2 );    an output transistor that has its gate electrically connected to said FD 1  and FD 2 , the combination of said FD 1 , FD 2 , and said gate of the output transistor forming an output node; and    a reset transistor coupled between a voltage reference and said output node.    
   
   
       2 . The apparatus of  claim 1  wherein the voltage reference is selectable between an off state V RST-OFF  or an on state V RST-ON .  
   
   
       3 . The apparatus of  claim 1  wherein said light sensing element is a photodiode, photogate, or pinned photodiode, or partially pinned photodiode.  
   
   
       4 . The apparatus of  claim 1 , wherein the output transistor is connected to the column readout line without the use of a row select transistor.  
   
   
       5 . The apparatus of  claim 1 , further wherein said FD 1  and FD 2  are two separate diffusion regions formed in said semiconductor substrate.  
   
   
       6 . The apparatus of  claim 1 , wherein said first pair of pixels and said second pair of pixels have mirror symmetry to each other about any portion of the output transistor.  
   
   
       7 . The apparatus of  claim 1 , wherein the pixels within said first pair of pixels have mirror symmetry to each other about said FD 1 .  
   
   
       9 . A method of forming a portion of a pixel array comprising: 
 forming a first pair of pixels in a semiconductor substrate that use a common column readout line, each of said pixels comprising:    (1) a light sensing element; and    (2) a transfer transistor that selectively allows the transfer of signal from said light sensing element to a first floating node (FD 1 );    forming a second pair of pixels in the semiconductor substrate that use the common column readout line, each of said pixels comprising:    (1) a light sensing element; and    (2) a transfer transistor that selectively allows the transfer of signal from said light sensing element to a second floating node (FD 2 );    forming an output transistor that has its gate electrically connected to said FD 1  and FD 2 , the combination of said FD 1 , FD 2 , and said gate of the output transistor being an output node; and    forming a reset transistor coupled between a voltage reference and said output node.    
   
   
       10 . The method of  claim 9  wherein the voltage reference is selectable between an off state V RST-OFF  or an on state V RST-ON .  
   
   
       11 . The method of  claim 9 , wherein the output transistor is connected to the column readout line without the use of a row select transistor.  
   
   
       12 . The method of  claim 9 , further including forming said FD  1  and FD 2  as two separate diffusion regions formed in said semiconductor substrate.  
   
   
       13 . The method of  claim 9 , wherein said first pair of pixels and said second pair of pixels have mirror symmetry to each other about any portion of the output transistor.  
   
   
       14 . The method of  claim 9 , wherein said first pair of pixels and said second pair of pixels have mirror symmetry to each other about any portion of the reset transistor.  
   
   
       15 . The method of  claim 9 , wherein the pixels within said first pair of pixels have mirror symmetry to each other about said FD  1 .  
   
   
       16 . A set of pixels in a pixel array comprising: 
 a first pair of adjacent pixels having mirror symmetry about an axis through a first floating node (FD 1 ), said first pair of adjacent pixels having a photodiode and a transfer gate;    a second pair of adjacent pixels having mirror symmetry about an axis through a second floating node (FD 2 ), said second pair of adjacent pixels having a photodiode and a transfer gate, wherein said first pair of adjacent pixels and said second pair of adjacent pixels are adjacent to each other and share a common readout line;    an amplifier transistor having its gate connected to FD 1  and FD 1  to form an output node; and    a reset transistor for resetting said output node to a reset voltage V RST .    
   
   
       17 . The set of pixels of  claim 16  wherein either said amplifier transistor or said reset transistor is located between said first pair of pixels and said second pair of pixels and there is mirror symmetry of said first pair of pixels and said second pair of pixels about an axis through said amplifier transistor or said reset transistor.  
   
   
       18 . The set of pixels of  claim 16  wherein the reset voltage is selectable between an off state V RST-OFF  or an on state V RST-ON .  
   
   
       19 . The set of pixels of  claim 16 , wherein the output transistor is connected to the readout line without the use of a row select transistor.  
   
   
       20 . The set of pixels of  claim 16 , further wherein said FD 1  and FD 2  are two separate diffusion regions formed in said semiconductor substrate.