Method and apparatus to execute an instruction with a semi-fast operation in a staggered ALU

Abstract

A method for executing an instruction with a semi-fast operation in a staggered ALU. The method of one embodiment comprises generating a first operation and a second operation from a micro-instruction. The first and second operations are scheduled for execution in a staggered arithmetic logic unit (ALU). The first and second operations are separated by N clock cycles. Data from the first operation is communicated to the second operation for use with execution of the second operation.

1 . A method comprising: 
 generating a first operation and a second operation from a micro-instruction;    scheduling said first and second operations for execution in a staggered arithmetic logic unit (ALU), wherein said first and second operations are separated by N clock cycles; and    communicating data from said first operation to said second operation for use with execution of said second operation.    
     
     
         2 . The method of  claim 1  wherein further comprising: 
 executing said first operation;    executing said second operation N clock cycles after execution of said first operation;    checking data from said first portion for correctness; and    detecting whether replay is needed for said first and second operations.    
     
     
         3 . The method of  claim 2  wherein said data communicated from said first operation is higher order bits of an operand of said slow micro-instruction, wherein said higher order bits are to be used in processing of lower order bits of said operand.  
     
     
         4 . The method of  claim 3  wherein said staggered ALU is a fast integer ALU.  
     
     
         5 . The method of  claim 4  wherein said micro-instruction is a shift right micro-instruction.  
     
     
         6 . The method of  claim 4  wherein said micro-instruction is a rotate micro-instruction.  
     
     
         7 . The method of  claim 2  wherein said data communicated from said first operation is flag bits of said first operation, wherein said flag bits are to be used in processing of lower order bits of an operand of said slow micro-instruction.  
     
     
         8 . The method of  claim 7  wherein said slow micro-instruction is a conditional move micro-instruction.  
     
     
         9 . The method of  claim 1  wherein N equals to two.  
     
     
         10 . A method comprising: 
 generating a first operation and a second operation from a complex micro-operation;    scheduling said first and second operations for execution in a staggered ALU, wherein said second operation is scheduled to execute M clock cycles after said first operation;    communicating resultant data from said first operation after execution of said first operation to logic for said second operation, wherein said resultant data is used to process a first portion of said second operation;    checking whether said resultant data is correct; and    executing said second operation with said resultant data.    
     
     
         11 . The method of  claim 10  further comprising: 
 determining whether a replay is necessary for said first and second operations; and    retiring said first and second operations.    
     
     
         12 . The method of  claim 11  wherein said first and second operations are each comprised of a first portion and a second portion, wherein lower order bits of an operand are processed during said first portion and higher order bits of said operand are processed during said second portion.  
     
     
         13 . The method of  claim 12  wherein M equals to two.  
     
     
         14 . The method of  claim 13  wherein said complex micro-instruction is either a shift right micro-instruction, a rotate micro-operation, or a byte swap micro-instruction.  
     
     
         15 . The method of  claim 11  wherein M equals to three.  
     
     
         16 . The method of  claim 15  wherein said complex micro-instruction is either a conditional move micro-instruction, check flags micro-instruction, or a branch micro-instruction.  
     
     
         17 . An apparatus comprising: 
 a scheduler to receive a first micro-instruction, said scheduler to generate a first operation and a second operation for said first micro-instruction, said scheduler to further schedule said first and second operations for execution N clock cycles apart; and    a staggered ALU coupled to said scheduler, said staggered ALU to execute said first and second operations, wherein said staggered ALU is comprised of a first logic to operate on lower order bits of an operand and a second logic to operate on high order bits of said operand and a flag logic to operate on flag bits, said staggered ALU wired to communicate results of said first operation from said second logic and said flag logic for use at said first logic by said second operation.    
     
     
         18 . The apparatus of  claim 17  wherein said staggered ALU is a fast integer ALU.  
     
     
         19 . The apparatus of  claim 18  further comprising an integer register file coupled to said staggered ALU and said scheduler, said integer register file to provide said operand.  
     
     
         20 . A processor comprising: 
 a scheduler to receive an instruction, said scheduler to generate a first operation and a second operation for said instruction, said scheduler to further schedule said first and second operations for execution N clock cycles apart, wherein said second operation is dependent on said first operation;    an execution unit coupled to said scheduler, said execution unit to execute said first and second operations, said execution unit wired to internally communicate data from said first operation for use on a subsequent clock cycle by said second operation;    an integer register file coupled to execution unit, said integer register file to provide an operand for said instruction; and    a cache memory coupled to said register file, said cache memory to provide data to said integer register file for processing in said execution unit.    
     
     
         21 . The processor of  claim 20  wherein said execution unit is comprised of a first logic to operate on lower order bits of said operand and a second logic to operate on high order bits of said operand and a flag logic to operate on flag bits.