Current mode output driver

Abstract

A current mode output driver and output current control method of controlling an output current using a gate voltage are provided. The current mode output driver, which outputs data read from a memory core to a transmission line, includes a gate voltage control circuit, a bias circuit, and a driver circuit. The gate voltage control circuit generates a predetermined gate voltage in response to a current control signal. The bias circuit outputs the gate voltage as a first enable signal in an active mode, and outputs a ground voltage as a second enable signal in a standby mode. The driver circuit drives a predetermined output current in response to the first enable signal, outputs the predetermined output voltage to the transmission line according to the data, and stops its operation in response to the second enable signal. The gate voltage control circuit changes the level of the gate voltage according to a value of the current control signal and output the changed result. Therefore, it is possible to easily increase resolution of an output current and reduce the occupied area of the current mode output driver, thereby facilitating a circuit design.

1 . An apparatus which outputs data from a memory to a transmission line, comprising: 
 at least one set of transistors, wherein: 
 each set of the at least one set of transistors comprises a first transistor and a second transistor coupled in series;  
 the gate of the first transistor receives data from the memory;  
 the drain of the second transistor is coupled to the transmission line; and  
 the gate of the second transistor receives a variable voltage signal to vary the resistance of the second transistor.  
   
   
   
       2 . The apparatus of  claim 1 , wherein the resistance of the second transistor is varied to match the impedance of the transmission line.  
   
   
       3 . The apparatus of  claim 1 , wherein the variable voltage signal is based on external feedback of the current level on the transmission line.  
   
   
       4 . The apparatus of  claim 1 , wherein the memory is random access memory.  
   
   
       5 . The apparatus of  claim 4 , wherein the random access memory is a dynamic random access memory.  
   
   
       6 . The apparatus of  claim 5 , wherein the dynamic random access memory is a rambus dynamic random access memory.  
   
   
       7 . The apparatus of  claim 5 , wherein at least one of the first transistor and the second transistor is a NMOS transistor.  
   
   
       8 . The apparatus of  claim 5 , wherein at least one of the first transistor and the second transistor is a PMOS transistor.  
   
   
       9 . The apparatus of  claim 1 , wherein the apparatus is a current mode output driver.