Multi-plane type flash memory and methods of controlling program and read operations thereof

Abstract

A multi-plain type flash memory device comprises a plurality of plains each including a plurality of memory cell blocks, page buffers each latching an input data bit to be output to its corresponding plain or latching an output data bit to be received from the corresponding plain, cache buffers each storing an input or output data bits in response to one of cache input control signals and each transferring the stored data bit to the page buffer or an external device in response to one of cache output control signals, and a control logic circuit generating the cache input and output control signals in response to command and chip enable signals containing plural bits. The program and read operations for the plural plains are conducted simultaneously in response to the chip enable signal containing the plural bits, which increases an operation speed and data throughput processed therein.

1 . A flash memory device comprising: 
 a plurality of plains each including a plurality of memory cell blocks;    a plurality page buffers, each page buffer arranged in correspondence with one of the plural plains, each page buffer latching an input data bit to be output to its corresponding plain or latching an output data bit to be received from the corresponding plain;    a plurality of cache buffers, each cache buffer arranged in correspondence with one of the page buffers, each cache buffer storing the input data bit or the latched output data bit in response to one of cache input control signals and each cache buffer transferring the stored data bit to the corresponding page buffer or an external device in response to one of cache output control signals; and    a control logic circuit generating the cache input and output control signals in response to command and chip enable signals containing plural bits.    
   
   
       2 . The flash memory device as set forth in  claim 1 , wherein the control logic circuit generates one among a program command, a read command, and an erase command in response to the command signal, and generates row and column address signals in response to an external address signal.  
   
   
       3 . The flash memory device as set forth in  claim 1 , wherein the number of bits of the chip enable signal is identical to the number of the plains.  
   
   
       4 . The flash memory device as set forth in  claim 2 , further comprising: 
 a high voltage generator generating bias voltages in response to one among the program voltage, the read command, and the erase command;    an X-decoder selecting one of the memory cell blocks included in each of the plains on basis of the row address signal and supplying the bias voltages to the selected memory cell block; and    a Y-decoder decoding the column address signal and applying the column address signal to the page buffers,    wherein the page buffers select bitlines of corresponding plains partially or entirely in response to the column decoding signal, and output the input data bits to the selected bitlines or latch the output data bits received from the selected bitlines.    
   
   
       5 . The flash memory device as set forth in  claim 2 , wherein the control logic circuit generates the program command when the command signal contains a page program setup code, and disables a ready/busy signal for a first predetermined time when receiving the command signal containing a confirmation code after generating the program command.  
   
   
       6 . The flash memory device as set forth in  claim 5 , wherein the control logic circuit, after generating the program command, enables the cache input control signals one by one in sequence for a second predetermined time when the plural bits are changed into a predetermined logic value one by one in sequence for the second predetermined time, and enables the cache output control signals at the same time while the ready/busy signal is being disabled when the plural bits are changed into the predetermined logic value at the same time for the first predetermined time; and 
 wherein the cache buffers stores the input data bits one by one in sequence when the cache input control signals are enabled one by one in sequence, and outputs the stored data bits to the page buffers at the same time when the cache output control signals are enabled at the same time.    
   
   
       7 . The flash memory device as set forth in  claim 6 , wherein after storing the input data bits stored in the last one of the cache buffers, the plural bits are changed to the predetermined logic value at the same time for the first predetermined time.  
   
   
       8 . The flash memory device as set forth in  claim 2 , wherein the control logic circuit generates the read command when the command signal contains a read code, and disables a ready/busy signal for a first predetermined time when the external address signal is received after generating the read command.  
   
   
       9 . The flash memory device as set forth in  claim 8 , wherein the control logic circuit, after generating the read command, enables the cache input control signals at the same time while the ready/busy signal is being disabled, and enables the cache output control signals one by one in sequence for a second predetermined time when the plural bits are changed into a predetermined logic value one by one in sequence for the second predetermined time; and 
 wherein the cache buffers store the latched output data bits received from the page buffers when the cache input control signals are enabled at the same time, and output the stored data bits to the external device one by one in sequence when the cache output control signals are enabled one by one in sequence.    
   
   
       10 . The flash memory device as set forth in  claim 9 , wherein the plural bits are changed into the predetermined logic value when the control logic circuit receives the command signal, being maintained in the predetermined logic value when the ready/busy signal is being disabled.  
   
   
       11 . The flash memory device as set forth in  claim 9 , wherein the plural bits are changed into the predetermined logic value one by one in sequence for the second predetermined time after the latched output data bits are sequentially stored in the cache buffers.  
   
   
       12 . A method of controlling a program operation of a multi-plain type flash memory device, the method comprising: 
 generating a program command in response to a command signal;    storing input data bits into cache buffers arranged in correspondence with a plurality of plains;    generating bias voltages for the program operation in response to the program command;    selecting one of memory cell blocks of each of the plural plains according to row and column address signals;    applying the bias voltages to the selected memory cell block; and    outputting data bits stored in the cache buffers to the plural plains.    
   
   
       13 . The method as set forth in  claim 12 , wherein the storing-input-data-bits step comprises: 
 enabling cache input control signals one by one in sequence for a predetermined time in response to a chip enable signal;    storing the input data bits in a corresponding one of the cache buffers in response to one of the cache input control signals; and    repeating the enabling-cache-input-control-signals step and storing-the -input-data-bits step until the input data bits are stored up to the last one of the cache buffers.    
   
   
       14 . The method as set forth in  claim 13 , wherein the enabling step comprises: changing bits of the chip enable signal into a predetermined logic value one by one in sequence for the predetermined time after generation of the program command.  
   
   
       15 . The method as set forth in  claim 13 , wherein the storing-input-data-bits step further comprises: changing bits of the chip enable signal into a predetermined logic value simultaneously for a predetermined time after the input data bits are stored up to the last one of the cache buffers.  
   
   
       16 . The method as set forth in  claim 12 , wherein the outputting step comprises: 
 enabling cache output control signals simultaneously, when bits of a chip enable signal are changed into a predetermined logic value simultaneously for a first predetermined time, for a second predetermined time after generation of the program command;    outputting data bits stored in the cache buffers to page buffers that are each coupled to at least one of the cache buffers and arranged in correspondence with the plural plains, in response to the cache output control signals; and    latching the stored data bits each in the page buffers and outputting the latched data bits each to the plural plains.    
   
   
       17 . A method of controlling a read operation of a multi-plain type flash memory device, the method comprising: 
 generating a read command in response to a command signal;    generating bias voltages for the read operation in response to the read command;    selecting one of memory cell blocks of each of the plural plains according to row and column address signals;    applying the bias voltages to the selected memory cell block;    storing output data bits of the plural plains simultaneously in cache buffers arranged in correspondence with the plural plains; and    outputting data bits stored in the cache buffers to an external device one by one in sequence.    
   
   
       18 . The method as set forth in  claim 17 , wherein the step of storing comprises: 
 latching the output data bits in page buffers arranged in correspondence with the plural plains;    enabling cache input control signals at the same time when a ready/busy signal is disabled after generation of the read command; and    storing the latched data bits simultaneously in the cache buffers coupled to the page buffers in response to the cache input control signals.    
   
   
       19 . The method as set forth in  claim 18 , wherein the step of enabling comprises: changing bits of the chip enable signal simultaneously into a predetermined logic value when the read command is generated and maintaining the bits in the predetermined logic value while the ready/busy signal is being disabled.  
   
   
       20 . The method as set forth in  claim 17 , wherein the step of outputting comprises: 
 enabling cache output control signals one by one in sequence for a predetermined time in response to bits of a chip enable signal;    outputting the data bit, which is stored in corresponding to one of the cache buffers, to the external device in response to an enabled one of the cache output control signals; and    repeating the enabling-cache-output-control-signals step and outputting step until the data bit stored in the last one of the cache buffers is output to the external device.    
   
   
       21 . The method as set forth in  claim 20 , wherein the step of enabling further comprises: changing bits of the chip enable signal into a predetermined logic value one by one in sequence for the predetermined time after the output data bits are simultaneously stored in the cache buffers.