US2006202334A1PendingUtilityA1

Method of forming redistribution bump and semiconductor chip and mount structure fabricated using the same

Assignee: SAMSUNG ELECTRONICS CO LTDPriority: Jul 23, 2003Filed: Jun 1, 2006Published: Sep 14, 2006
Est. expiryJul 23, 2023(expired)· nominal 20-yr term from priority
H10W 72/952H10W 72/923H10W 72/251H10W 72/29H10W 70/05H10W 74/129H10W 72/20H10W 72/922H10W 70/68H10W 72/012H10W 72/074H10W 72/244H10W 72/019H10W 72/071
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Claims

Abstract

Provided are a method of forming a bump whose upper surface is substantially flat and whose area can be enlarged in a uniform pad pitch to simplify mounting a liquid crystal display drive IC (LDI) and a semiconductor chip and a mount structure using the method to minimize a pad area inside the chip. Thus, the pad area on an edge of a conventional chip is minimized and the bump is formed in a substantially flat location inside the chip and an electrical connection between the pad and the bump is performed by a redistribution metal line.

Claims

exact text as granted — not AI-modified
1 . A semiconductor chip mounted on an external electronic device, the semiconductor chip comprising: 
 a bump coupled between a semiconductor chip pad and an external electronic device,    wherein the bump having a substantially flat upper surface is formed in a substantially flat location beyond a location of a pad and is connected to the pad via a redistribution metal line.    
     
     
         2 . The semiconductor chip of  claim 1 , wherein the pad and the bump have at least one layered substantially flat passivation film formed therebetween.  
     
     
         3 . The semiconductor chip of  claim 1 , wherein the bump is made of one of gold and a gold alloy.  
     
     
         4 . The semiconductor chip of  claim 1 , wherein the redistribution metal line covering the upper portion of the pad is extended under the bump.  
     
     
         5 . The semiconductor chip of  claim 1 , wherein the redistribution metal line is made by layering one selected from the group consisting of TiW, Au, Cr, Cu, Ti, Ni, NiV, Pd, or a compound line made of at least two of the eight materials.  
     
     
         6 . The semiconductor chip of  claim 1 , wherein the redistribution metal line and the bump have an additional redistribution metal line formed therebetween.  
     
     
         7 . The semiconductor chip of  claim 6 , wherein the additional redistribution metal line is made of one selected from the group consisting of Au, an Au alloy, and Ni/Au.  
     
     
         8 . A semiconductor chip comprising: 
 a substrate having a pad formed thereon;    a first passivation film overlying the chip and partially exposing an upper portion of the pad;    a second passivation film formed on the first passivation film to expose the upper portion of the pad and a portion of the first passivation film;    a bump having a substantially flat surface on the upper portion of the second passivation film in a substantially flat location detached from a location of the pad;    a redistribution metal line extending from the upper portion of the pad to a lower portion of the bump for an electrical connection between the pad and the bump; and    a third passivation film exposing the bump and protecting the redistribution metal line.    
     
     
         9 . The semiconductor chip of  claim 8 , wherein the bump is made of one of gold and a gold alloy.  
     
     
         10 . The semiconductor chip of  claim 8 , wherein the redistribution metal line is made by layering one selected from the group consisting of TiW, Au, Cr, Cu, Ti, Ni, NiV, Pd, or a compound line made of at least two of the eight materials.  
     
     
         11 . The semiconductor chip of  claim 8 , wherein the redistribution metal line and bump have an additional redistribution metal line formed therebetween.  
     
     
         12 . The semiconductor chip of  claim 11 , wherein the additional redistribution metal line is made of one selected from the group consisting of Au, an Au alloy, and Ni/Au.  
     
     
         13 . A mount structure comprising the semiconductor chip of  claim 8  mounted on a liquid crystal panel (LCP), in which the bump and an electrode of the LCP are connected.  
     
     
         14 . The mount structure of  claim 13 , wherein the semiconductor chip and the LCP are attached together with an anisotropic conductive film or non-conductive adhesive.  
     
     
         15 . A mount structure comprising the semiconductor chip of  claim 8  mounted on a film in which a circuit pattern is made and including the circuit pattern in which the bump and the circuit pattern of the film are connected.  
     
     
         16 . A system comprising: 
 a liquid crystal panel (LCP) having an electrode; and    a semiconductor chip having a semiconductor chip pad, the semiconductor chip including a bump coupled between a semiconductor chip pad and the electrode of the LCP, wherein the bump having a substantially flat upper surface is formed in a substantially flat location beyond a location of the pad and is connected to the pad via a redistribution metal line.

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