Semiconductor structure and method of fabrication

Abstract

Fabricating a semiconductor includes depositing a metal layer outwardly from a dielectric layer and forming a mask layer outwardly from a first portion of the metal layer. Atoms are incorporated into an exposed second portion of the metal layer to form a composition-altered portion of the metal layer. The mask layer is removed from the first portion of the metal layer and a barrier layer is deposited outwardly from the metal layer. A poly-Si layer is deposited outwardly from the barrier layer to form a semiconductor layer, where the barrier layer substantially prevents reaction of the metal layer with the poly-Si layer. The semiconductor layer is etched to form gate stacks, where each gate stack operates according to one of a plurality of work functions.

1 - 10 . (canceled)  
   
   
       11 . A semiconductor structure, comprising: 
 a dielectric layer;    a metal layer disposed outwardly from the dielectric layer, the metal layer comprising a first portion and a composition-altered portion;    a barrier layer disposed outwardly from the metal layer;    a poly-Si layer deposited outwardly from the barrier layer, the barrier layer operable to prevent diffusion and reaction between the metal layer and the poly-Si layer;    a first stack structure comprising the first portion of the metal layer and operating according to a first work function; and    a second stack structure comprising the composition-altered portion of the metal layer and operating according to a second work function.    
   
   
       12 . The semiconductor structure of  claim 11 , wherein the metal layer has a thickness in a range between one monolayer and 500 angstroms.  
   
   
       13 . The semiconductor structure of  claim 11 , wherein the metal layer comprises molybdenum.  
   
   
       14 . The semiconductor structure of  claim 11 , wherein the composition-altered metal layer comprises molybdenum nitride (MoN).  
   
   
       15 . The semiconductor structure of  claim 11 , wherein the composition-altered portion of the metal layer comprises a plurality of atoms incorporated using at least one of an ion implantation, direct plasma nitridation, a remote plasma nitridation, an ammonia anneal, an S i H 4  anneal, and Si 2 H 6  anneal.  
   
   
       16 . The semiconductor structure of  claim 11 , wherein the plurality of atoms comprises a plurality of nitrogen ions.  
   
   
       17 . The method of claim  10 , wherein the plurality of atoms comprises a plurality of silicon atoms.  
   
   
       18 . The semiconductor structure of  claim 11 , wherein the barrier layer has a thickness in a range between 25 angstroms and 100 angstroms.  
   
   
       19 . The semiconductor structure of  claim 11 , wherein the barrier layer comprises a compound selected from one of a titanium nitride (TiN) compound, a tantalum nitride (TaN) compound, a molybdenum nitride (MoN) compound, a hafnium nitride (HfN) compound, and a zirconium nitride (ZrN) compound.  
   
   
       20 . The semiconductor structure of  claim 11 , wherein: 
 the first work function corresponds to a p-channel metal oxide semiconductor (PMOS); and    the second work function corresponds to a n-channel metal oxide semiconductor (NMOS).    
   
   
       21 - 23 . (canceled)