Backend metallization method and device obtained therefrom

Abstract

A semiconductor device and a method of making it are described. During the formation of the semiconductor device, a hard mask is formed of an etch-resistant material. The mask prevents etchant from etching an area within a dielectric material near a conductive plug. The mask may be formed of a nitride. Conductive material is then deposited withinan etched via and is contacted with the conductive plug.

1 - 38 . (canceled)  
   
   
       39 . A semiconductor device comprising: 
 an insulator layer;    a conductive plug positioned within said insulator layer and formed of a single conductive material;    a doped region connected to said conductive plug;    a non-conductive layer having an etched via formed at least partially over said conductive plug, wherein a first portion of said etched via is wider in diameter than said conductive plug; and    a conductive connector formed in said via in electrical contact with said plug and including a first conductive layer deposited in and in contact with said etched via and a second conductive layer deposited over and in contact with said first conductive layer, said first conductive layer including a portion in contact with said conductive plug.    
   
   
       40 . The semiconductor structure of  claim 39 , further comprising an etch-stop layer located on said insulator layer and surrounding said plug.  
   
   
       41 . The semiconductor structure of  claim 40 , further comprising an wherein said etch-stop layer comprises silicon nitride.  
   
   
       42 . The semiconductor structure of  claim 40 , wherein said etch-stop layer comprises silicon carbide.  
   
   
       43 . The semiconductor structure of  claim 40 , wherein said etch-stop layer comprises silicon dioxide.  
   
   
       44 . The semiconductor structure of  claim 40 , wherein said etch-stop layer comprises silicon nitride and silicon carbide.  
   
   
       45 . The semiconductor structure of  claim 40 , wherein said non-conductive layer comprises doped silicate glass.  
   
   
       46 . The semiconductor structure of  claim 45 , wherein said doped silicate glass comprises borophosphosilicate glass.  
   
   
       47 . The semiconductor structure of  claim 40 , wherein said first conductive layer comprises one or more materials selected from the group consisting of aluminum, copper, doped polysilicate, tantalum, tantalum nitride, titanium, titanium nitride and tungsten.  
   
   
       48 . The semiconductor structure of  claim 40 , further comprising a substrate with a connection region, wherein said conductive plug is provided over said connection region.  
   
   
       49 . A semiconductor device comprising: 
 at least one memory cell comprising:    an active region in a substrate;    a conductive plug formed of a single conductive material positioned within an insulator layer and provided over said active region, said conductive plug    being electrically connected with said active region;    an intermediate non-conductive layer provided over said insulator layer having an etched via over said plug, said etched via having a first via portion wider in diameter than said conductive plug, and a second via portion above said first via portion having a greater diameter than said first via portion; and    a first conductive layer deposited in and in contact with said first and second via portions, said first conductive layer including a portion in contact with said conductive plug, and a second conductive layer deposited over and in contact with said first conductive layer.    
   
   
       50 . The semiconductor memory device of  claim 49 , wherein said intermediate layer comprises doped silicate glass.  
   
   
       51 . The semiconductor memory device of  claim 50 , wherein said doped silicate glass comprises borophosphosilicate glass.  
   
   
       52 . The semiconductor memory device of  claim 49 , wherein said first conductive layer comprises one or more materials selected from the group consisting of aluminum, copper, doped polysilicate, tantalum, tantalum nitride, titanium, titanium nitride and tungsten.  
   
   
       53 . The semiconductor memory device of  claim 49 , wherein said second conductive layer comprises one or more materials selected from the group consisting of aluminum, copper, doped polysilicate, tantalum, tantalum nitride, titanium, titanium nitride and tungsten.  
   
   
       54 . The semiconductor memory device of  claim 49 , further comprising a plurality of said memory cells.  
   
   
       55 . The semiconductor memory device of  claim 54 , wherein said plurality of said memory cells are in an array.  
   
   
       56 . A processor-based system comprising: 
 a processing unit;    a semiconductor circuit coupled to said processing unit, said semiconductor circuit comprising:    a conductive plug formed of a single conductive material positioned within an insulator and provided on a connection region;    an intermediate non-conductive layer provided over said insulator having at least an etched via over said conductive plug, said etched via having a first via portion being wider in diameter than said conductive plug, and a second via portion above said first via portion having a greater diameter than said first via portion; and    a conductive connector electrically coupled to said connection region, said conductive connector comprising a first conductive layer deposited in and in contact with said first and second via portions, said first conductive layer including a portion in contact with said conductive plug, and a second conductive layer deposited over and in contact with said first conductive layer.    
   
   
       57 . The processor-based system of  claim 56 , wherein said connection region comprises a doped region within said substrate.  
   
   
       58 . The processor-based system of  claim 56 , wherein said intermediate layer comprises doped silicate glass.  
   
   
       59 . The processor-based system of  claim 58 , wherein said doped silicate glass comprises borophosphosilicate glass.  
   
   
       60 . The processor-based system of  claim 56 , wherein said first conductive layer comprises at least one layer of one or more materials selected from the group consisting of aluminum, copper, doped polysilicate, tantalum, tantalum nitride, titanium, titanium nitride and tungsten.  
   
   
       61 . The processor-based system of  claim 56 , wherein said second conductive layer comprises at least one layer of one or more materials selected from the group consisting of aluminum, copper, doped polysilicate, tantalum, tantalum nitride, titanium, titanium nitride and tungsten.  
   
   
       62 . The processor-based system of  claim 56 , further comprising a substrate, and wherein said connection region is located in said substrate, and wherein said conductive plug is located over said connection region.  
   
   
       63 . A method of making a semiconductor device, said method comprising: 
 forming a layer of insulating material over a substrate;    forming a conductive plug within said first layer of insulating material, wherein said conductive plug consists essentially of a single conductive material;    forming a second layer of insulating material over said conductive plug; and    etching said second layer of insulating material to said conductive plug and etch-stop layer to form a via having first and second via portions, wherein said first via portion is wider than the conductive plug's width, and said second via portion is wider than said first via portion.    
   
   
       64 . The method of  claim 63 , further comprising depositing at least a first conductive layer in said first and second via portions.  
   
   
       65 . The method of  claim 64 , comprising depositing a second conductive layer over said first conductive layer in said first and second via portions.  
   
   
       66 . The method of  claim 63 , wherein said plug is formed by: 
 forming an opening in said first layer of insulating material;    depositing a conductive material on said first layer of insulating material, filling said opening; and    abrading said conductive material from the top surface of said first layer of insulating such that only conductive material within said opening remains.    
   
   
       67 . The method of  claim 66 , wherein said abrading comprises chemical-mechanical polishing of said conductive material.  
   
   
       68 . The method of  claim 66 , wherein said conductive plug is connected to a doped region in said substrate.  
   
   
       69 . A method of making a semiconductor device, said method comprising: 
 forming a first non-conductive layer over a substrate;    forming a conductive plug within said first non-conductive layer, wherein said conductive plug consists essentially of a single conductive material;    forming a second non-conductive layer over said conductive plug;    forming a via having first and second via portions by etching said second non-conductive layer to said conductive plug and etch-stop layer, wherein said first via portion is wider in diameter than said conductive plug; and    depositing a conductive material within said first and second via portions.    
   
   
       70 . A method of making a semiconductor device, said method comprising: 
 forming an active region in a semiconductor substrate;    forming a first insulator layer over said active region;    forming a single conductive material within said first insulator layer, wherein said conductive material is electrically connected with said active region;    forming a second insulator layer over said conductive material;    forming a via having first and second via portions within said second insulator layer, wherein said first via portion is wider in diameter than said conductive material, and wherein said second via portion is wider in diameter than said first via portion; and    forming a conductive connector in said first and second via portions that are in electrical contact with said conductive material.