Methods for forming double gate strained-semiconductor-on-insulator device structures

Abstract

The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

1 - 26 . (canceled)  
   
   
       27 . A method for forming a structure, the method comprising: 
 forming a substrate having a first gate electrode layer disposed over a substrate insulator layer, a first gate insulator layer disposed over the first gate electrode layer, and a strained semiconductor layer disposed over the first gate insulator layer;    forming a second gate insulator layer over the strained semiconductor layer;    forming a second gate electrode layer over the second gate insulator layer;    defining a second gate electrode by removing a portion of the second gate insulator electrode layer; and    defining a first gate electrode by removing a portion of the first gate electrode layer.    
   
   
       28 . The method of  claim 27 , wherein the strained semiconductor layer is tensilely strained.  
   
   
       29 . The method of  claim 28 , wherein the strained semiconductor layer comprises tensilely strained silicon.  
   
   
       30 . The method of  claim 27 , wherein the strained semiconductor layer is compressively strained.  
   
   
       31 . The method of  claim 30 , wherein the strained semiconductor layer comprises compressively strained germanium.  
   
   
       32 . The method of  claim 27 , further comprising: 
 forming a dielectric sidewall spacer proximate the second gate electrode; and    forming a conductive sidewall spacer proximate the dielectric sidewall spacer.    
   
   
       33 . The method of  claim 27 , further comprising: 
 defining a source in the strained semiconductor layer.    
   
   
       34 . The method of  claim 27 , further comprising: 
 defining a drain in the strained semiconductor layer.    
   
   
       35 - 62 . (canceled)  
   
   
       63 . The method of  claim 27 , further comprising: 
 forming a dielectric sidewall spacer proximate the second gate electrode; and    removing a portion of the strained semiconductor layer and a portion of the first gate insulator layer to define a vertical structure disposed over the substrate insulator layer, the vertical structure including a strained layer region, a first gate insulator region, and a first gate electrode layer region disposed under the second gate electrode,    wherein defining the first gate electrode comprises laterally shrinking the first gate electrode layer region.    
   
   
       64 . The method of  claim 27 , wherein the strained semiconductor layer comprises at least one of a group II, a group m, a group IV, a group V, and a group VI element.  
   
   
       65 . The method of  claim 64 , wherein the strained semiconductor layer comprises a material selected from the group consisting of gallium arsenide, indium phosphide, and zinc selenide.  
   
   
       66 . The method of  claim 27 , wherein the first gate insulator layer comprises a material having a dielectric constant higher than a dielectric constant of silicon dioxide.  
   
   
       67 . The method of  claim 27 , wherein the second gate insulator layer comprises a material having a higher dielectric constant higher than a dielectric constant of silicon dioxide.  
   
   
       68 . The method of  claim 27 , wherein the first gate electrode comprises a conductive material.  
   
   
       69 . The method of  claim 68 , wherein the conductive material is selected from the group consisting of doped polycrystalline silicon and a metal.  
   
   
       70 . The method of  claim 27 , wherein the second gate electrode comprises a conductive material.  
   
   
       71 . The method of  claim 70 , wherein the conductive material is selected from the group consisting of doped polycrystalline silicon and a metal.  
   
   
       72 . The method of  claim 27 , wherein the strained semiconductor layer is disposed between and in contact with the first gate insulator layer and the second gate insulator layer.  
   
   
       73 . The method of  claim 27 , wherein forming the substrate comprises: 
 forming the strained semiconductor layer over a relaxed semiconductor layer;    forming the first gate dielectric layer over the strained semiconductor layer;    forming the first gate electrode layer over the first gate dielectric layer;    bonding the first gate electrode layer to the substrate dielectric layer; and    removing the relaxed semiconductor layer.