Double gate strained-semiconductor-on-insulator device structures

Abstract

The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

1 - 12 . (canceled)  
   
   
       13 . A structure comprising: 
 a dielectric layer disposed over a substrate; and    a transistor formed over the dielectric layer, the transistor including: 
 a first gate electrode disposed over the dielectric layer;  
 a strained semiconductor layer disposed over the first gate electrode; and  
 a second gate electrode disposed over the strained semiconductor layer and  
   disposed over the first gate electrode.    
   
   
       14 . The structure of  claim 13 , wherein the strained semiconductor layer comprises at least one of a group II, a group III, a group IV, a group V, and a group VI element.  
   
   
       15 . The structure of  claim 13 , wherein the strained semiconductor layer is tensilely strained.  
   
   
       16 . The structure of  claim 15 , wherein the strained semiconductor layer comprises tensilely strained silicon.  
   
   
       17 . The structure of  claim 13 , wherein the strained semiconductor layer is compressively strained.  
   
   
       18 . The structure of  claim 17 , wherein the strained semiconductor layer comprises compressively strained germanium.  
   
   
       19 . The structure of  claim 13 , wherein the strained semiconductor layer has a strain level greater than 10 −3 .  
   
   
       20 . The structure of  claim 13 , further comprising: 
 a first gate insulator layer disposed between the first gate electrode and the strained semiconductor layer.    
   
   
       21 . The structure of  claim 20 , further comprising: 
 a second gate insulator layer disposed between the strained semiconductor layer and the second gate electrode.    
   
   
       22 . The structure of  claim 13 , wherein the strained semiconductor layer comprises a source and a drain.  
   
   
       23 . (canceled)  
   
   
       24 . The structure of  claim 13 , further comprising: 
 a sidewall spacer disposed proximate the second gate electrode.    
   
   
       25 . The structure of  claim 24 , wherein the sidewall spacer comprises a dielectric material.  
   
   
       26 . The structure of  claim 24 , wherein the sidewall spacer comprises a conductive material.  
   
   
       27 - 62 . (canceled)  
   
   
       63 . The structure of  claim 13 , wherein the first gate electrode is in contact with the dielectric layer.  
   
   
       64 . The structure of  claim 13 , wherein the first gate electrode comprises a conductive material.  
   
   
       65 . The structure of  claim 64 , wherein the conductive material is selected from the group consisting of doped polycrystalline silicon and a metal.  
   
   
       66 . The structure of  claim 13 , wherein the second gate electrode comprises a conductive material.  
   
   
       67 . The structure of  claim 66 , wherein the conductive material is selected from the group consisting of polycrystalline silicon and a metal.  
   
   
       68 . The structure of  claim 21 , wherein the first gate insulator layer comprises a material having a higher dielectric constant higher than a dielectric constant of silicon dioxide.  
   
   
       69 . The structure of  claim 21 , wherein the first gate insulator layer is in contact with the strained semiconductor layer.  
   
   
       70 . The structure of  claim 21 , wherein the second gate insulator layer comprises a material having a higher dielectric constant higher than a dielectric constant of silicon dioxide.  
   
   
       71 . The structure of  claim 21 , wherein the second gate insulator layer is in contact with the strained semiconductor layer.