Methods for forming strained-semiconductor-on-insulator bipolar device structures

Abstract

The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

1 - 46 . (canceled)  
   
   
       47 . A method for forming a structure, the method comprising: 
 providing a substrate having a strained semiconductor layer disposed over a dielectric layer;    defining a collector in a portion of the strained semiconductor layer;    depositing a material over the strained semiconductor layer;    forming a base in the material deposited over the strained semiconductor layer and in contact with the collector; and    forming an emitter over the base.    
   
   
       48 . The method of  claim 47 , wherein the strained semiconductor layer is tensilely strained.  
   
   
       49 . The method of  claim 48 , wherein the strained semiconductor layer comprises tensilely strained silicon.  
   
   
       50 . The method of  claim 47 , wherein the strained semiconductor layer is compressively strained.  
   
   
       51 - 62 . (canceled)  
   
   
       63 . The method of  claim 47 , wherein the strained semiconductor layer is in contact with the dielectric layer.  
   
   
       64 . The method of  claim 47 , wherein depositing the material over the strained semiconductor layer comprises a chemical vapor deposition step.  
   
   
       65 . The method of  claim 64 , wherein the chemical vapor deposition step is selected from the group consisting of atmospheric-pressure chemical vapor deposition, low-pressure chemical vapor deposition, and ultra-high-vacuum chemical vapor deposition.  
   
   
       66 . The method of  claim 47 , wherein depositing the material comprises selective deposition.  
   
   
       67 . The method of  claim 47 , wherein forming the base comprises doping the base by introducing dopants.  
   
   
       68 . The method of  claim 67 , wherein dopants are introduced during the deposition of the material over the strained semiconductor layer.  
   
   
       69 . The method of  claim 67 , wherein the dopants are introduced after the deposition of the material over the strained semiconductor layer.  
   
   
       70 . The method of  claim 69 , wherein the dopants are introduced by implantation.  
   
   
       71 . The method of  claim 47 , wherein defining the collector comprises introducing dopants into the portion of the strained semiconductor layer.  
   
   
       72 . The method of  claim 47 , further comprising: 
 forming a masking layer over the collector; and    removing a portion of the masking layer to expose a portion of the collector,    wherein forming the base comprises deposition of the material over the exposed portion of the collector and a remaining portion of the masking layer.    
   
   
       73 . The method of  claim 72 , further comprising removing the material deposited over the remaining portion of the masking layer.  
   
   
       74 . The method of  claim 47 , wherein the base material deposited over the strained semiconductor layer comprises a substantially relaxed semiconductor material.  
   
   
       75 . The method of  claim 74 , wherein the substantially relaxed semiconductor material comprises at least one of silicon and germanium.  
   
   
       76 . The method of  claim 47 , wherein the base material deposited over the strained semiconductor material comprises a compressively strained semiconductor material.  
   
   
       77 . The method of  claim 76 , wherein the compressively strained semiconductor material comprises at least one of silicon and germanium.  
   
   
       78 . The method of  claim 47 , wherein the base material deposited over the strained semiconductor material comprises a tensilely strained semiconductor material.  
   
   
       79 . The method of  claim 78 , wherein the tensilely strained semiconductor material comprises at least one of silicon and germanium.