Application of single exposure alternating aperture phase shift mask to form sub 0.18 micron polysilicon gates

Abstract

In accordance with the objects of this invention, a new method of fabricating a polysilicon gate transistor is achieved. An alternating aperture phase shift mask (AAPSM) is used to pattern polysilicon gates in a single exposure without a trim mask. A semiconductor substrate is provided. A gate dielectric layer is deposited. A polysilicon layer is deposited. The polysilicon layer, the gate dielectric layer and the semiconductor substrate are patterned to form trenches for planned shallow trench isolations (STI). A trench oxide layer is deposited filling the trenches. The trench oxide layer is polished down to the top surface of the polysilicon layer to complete the STI. A photoresist layer is deposited and patterned to form a feature mask for planned polysilicon gates. The patterning is by a single exposure using an AAPSM mask. Unwanted features in the photoresist pattern that are caused by phase conflicts overlie the STI. The polysilicon layer is etched to form the polysilicon gates.

1 . A method of fabricating a clear field alternating aperture phase shifting mask (AAPSM) for use in forming polysilicon gate transistors in the manufacture of an integrated circuit device comprising: 
 providing an opaque layer overlying a transparent substrate;    patterning said opaque layer to form opaque features corresponding to planned transistor gates wherein said opaque features overlap boundaries of planned active areas onto planned shallow trench isolation areas and wherein said opaque layer is removed from all other areas; and    forming a phase shifting layer in a part of said transparent substrate adjacent to said opaque features wherein said phase shifting layer overlies a part of said planned active areas on one side of each said planned transistors gate, wherein said phase shifting layer overlaps said boundaries of said planned active areas onto said planned shallow trench isolation areas, and wherein unwanted features caused by phase conflicts overlie said planned shallow trench isolations.    
   
   
       2 . The method according to  claim 1  wherein said phase shifting layer produces a 180 degree phase shift with respect to said transparent substrate.  
   
   
       3 . The method according to  claim 1  wherein said step of forming said phase shifting layer is by a subtractive process wherein said transparent substrate is etched.  
   
   
       4 . A method of fabricating a dark field alternating aperture phase shifting mask (AAPSM) for use in forming polysilicon gate transistors in the manufacture of an integrated circuit device comprising: 
 providing an opaque layer overlying a transparent substrate;    patterning said opaque layer to remove said opaque layer from planned active areas such that exposed said transparent substrate overlaps boundaries of said planned active areas onto planned shallow trench isolation areas and wherein said opaque layer remains in all other non-active areas to form opaque features corresponding to planned transistor gates; and    forming a phase shifting layer overlying a part of said transparent substrate adjacent to said opaque features wherein said phase shifting layer will overlie a part of said planned active areas on one side of each said planned transistors gate, wherein said phase shifting layer will overlap said boundaries of said planned active areas onto said planned shallow trench isolation areas, and wherein unwanted features caused by phase conflicts overlie said planned shallow trench isolations.    
   
   
       5 . The method according to  claim 4  wherein said phase shifting layer produces a 180 degree phase shift with respect to said transparent substrate.  
   
   
       6 . The method according to  claim 4  wherein said step of forming said phase shifting layer is by a subtractive process wherein said transparent substrate is etched.  
   
   
       7 . An alternating aperture phase shift mask for use in fabricating polysilicon gate transistors in the manufacture of an integrated circuit device comprising: 
 a transparent substrate;    a patterned opaque layer overlying said transparent substrate wherein said patterned opaque layer features correspond to planned transistor gates and overlap boundaries of planned active areas onto planned shallow trench isolation areas and wherein said patterned opaque layer is absent from all other areas; and    a patterned phase shifting layer overlying a part of said transparent substrate adjacent to said patterned opaque layer features wherein said phase shifting layer overlies a part of said planned active areas on one side of each said planned transistor gate, wherein said phase shifting layer overlaps said boundaries of said planned active areas onto said planned shallow trench isolation areas, and wherein unwanted features caused by phase conflicts overlie said planned shallow trench isolations.    
   
   
       8 . The method according to  claim 7  wherein said patterned phase shifting layer produces a 180 degree phase shift with respect to said transparent substrate.