Carrier for substrate film
Abstract
The invention relates to a carrier for supporting a substrate film during the chip-substrate assembly and bonding process. The carrier provides enhanced rigidity to the substrate film. The degree of rigidity and/or flexibility provided can be controlled by selection of the carrier dimensions, configuration and material choice. Advantages of embodiments of the carrier include easier handling, reduced probability of defective end products, and increased control in choosing the thinness of the substrate film. For example, the substrate film carrier can be used for lead-over-chip (LOC) assemblies and lead-under-chip (LUC) assemblies to create ball grid arrays (BGA), pin grid arrays (PGA), dual in-line packages (DIP), and the like.
Claims
exact text as granted — not AI-modified1 . A method of manufacturing integrated circuits, comprising:
forming a substrate film comprising a plurality of substrate units with each one of said substrate units comprising a substantially central cavity; interfacing a plurality of dies with a respective one of said substrate units by passing a plurality of wires through a respective one of said central cavities such that said wires connect to a first surface of said substrate film; connecting said dies to a second surface of said substrate film which is opposed to said first surface; forming a carrier comprising a pair of side bars connected to a plurality of cross bars and a pair of end bars; and connecting said carrier to selected portions of said first surface of said substrate film to enhance the rigidity of said film and group said substrate units into substrate sets.
2 . The method of claim 1 , wherein connecting said carrier comprises temporarily connecting at least a portion of said carrier to selected portions of said first surface of said substrate film.
3 . The method of claim 1 , wherein said method further comprises connecting said wires to said dies to electrically interface said dies with said substrate units.
4 . The method of claim 1 , wherein said method further comprises arranging said dies such that substantially central portions of said dies are exposed through said central cavities.
5 . The method of claim 1 , wherein said method further comprises arranging said side bars such that only one substrate unit is located along opposed length portions of said side bars.
6 . The method of claim 5 , wherein said method further comprises arranging said cross bars such that they separate adjacent sets.
7 . The method of claim 6 , wherein arranging said cross bars comprises arranging said cross bars such that at least one of said substrate sets comprises three substrate units.
8 . A method of manufacturing integrated circuits, comprising:
constructing a generally flat flexible tape comprising a plurality of substrate units with each being flanked by a pair of slots to facilitate removal and each having a cavity therebetween, said tape having a surface comprising a plurality of bonding pads associated with each of the substrate units; electrically interfacing a plurality of semiconductor chips with a respective one of said substrate units, said semiconductor chips having a plurality of bonding pads exposed through said cavities of said substrate units with lead wires passing through said cavities; connecting a temporary carrier to said surface of said flexible tape to provide support during a manufacturing process, said temporary carrier comprising a plurality of cross bars with adjacent cross bars having at least one of said substrate units positioned therebetween; transporting said carrier, said flexible tape and said semiconductor chips through said manufacturing process; and removing at least a portion of said carrier at completion of at least a portion of said manufacturing process.
9 . The method of claim 8 , wherein said method further comprises aligning a plurality of cross rails of said flexible tape with said cross bars of said carrier.
10 . The method of claim 8 , wherein said method further comprises forming said carrier with a plurality of layers.
11 . The method of claim 10 , wherein forming said carrier with a plurality of layers comprises forming said carrier with at least one of copper, polyimide and solder resist.
12 . The method of claim 8 , wherein said method further comprises arranging said semiconductor chips such that said chips comprise lead-over-chips (LOC).
13 . The method of claim 8 , wherein said method further comprises forming said carrier as an integral unit.
14 . The method of claim 8 , wherein said method further comprises forming said carrier and said flexible tape as an integral unit.
15 . The method of claim 14 , wherein forming said carrier and said flexible tape as an integral unit comprises molding said carrier and said flexible to form said integral unit.
16 . A method of manufacturing integrated circuits, comprising:
forming a substrate film comprising a first side rail, a second side rail and a plurality of substrate units therebetween, each of said substrate units including a plurality of bonding pads on a surface of said substrate film and a generally central cavity, said first side rail including a plurality of spaced first projecting portions and said second side rail including a plurality of spaced second projecting portions electrically interfacing a plurality of semiconductor dies to a respective one of said substrate units with lead wires that connect to bonding pads of said dies and that pass through said cavities and connect to said bonding pads of said substrate film; and connecting a carrier to said surface of said substrate film to support said substrate film and provide rigidity during at least a portion of a manufacturing process, said carrier comprising a first side bar substantially aligned with said first side rail of said substrate film and a second side bar substantially aligned with said second rail of said substrate film, said first side bar including a plurality of spaced first teeth substantially aligned with said first projecting portions and said second side bar including a plurality of second teeth substantially aligned with said second projecting portions.
17 . The method of claim 16 , wherein said method further comprises forming said carrier with at least two discrete layers with each layer comprising a different material.
18 . The method of claim 17 , wherein said method further comprises forming said carrier with at least one indexing hole that extends through said layers.
19 . The method of claim 16 , wherein said method further comprises arranging said semiconductor dies such that said bonding pads of said dies are exposed through said cavities of said units.
20 . The method of claim 16 , wherein said method further comprises attaching said dies to a surface of said substrate film that is opposed to the surface to which said carrier is connected.Join the waitlist — get patent alerts
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