Method and system for transmission and reception of asynchronously multiplexed signals

Abstract

A storage circuit defines a first field for storing first header bits of a first payload signal of a first data unit, a second field, and a third field for storing the first payload signal. The first header bits are equal in number to second header bits of a second payload signal of a second data unit. A division circuit divides the first header bits by a generator polynomial to produce a first error check code. The same generator polynomial is used to divide the second header bits to produce a second error check code. A remainder of division of hypothetical header bits by the generator polynomial is summed to the first error check code to produce a sum which is inserted into the second field of the storage circuit. The hypothetical header bits are greater in number than a total number of bits in the first and second fields, so that the first and second data units can be distinguished from each other by different error check results of the first and second data units.

1 - 46 . (canceled)  
   
   
       47 . A computer readable medium for a communications unit having circuitry operable to communicate using a data unit stored by the computer readable medium, the data unit comprising: 
 a header containing a plurality of first header bits of a payload signal and a first error check code representing a sum of the remainder of division of said first header bits by a generator polynomial and the remainder of division of hypothetical header bits by said generator polynomial, said hypothetical header bits being greater in number than said first header bits, whereby said data unit can be distinguished from another data unit containing second header bits of a second payload signal equal in number to said first header bits and a second error check code resulting from division of the second header bits by said generator polynomial; and    a payload field following said header for carrying said payload signal.    
   
   
       48 . The computer readable medium of  claim 47 , wherein said hypothetical header bits comprise higher-significant bits of non-zero value and all-zero lower significant bits equal in number to said first header bits plus the first error check code.  
   
   
       49 . The computer readable medium of  claim 48 , wherein said hypothetical header bits correspond in number to the maximum degree of an irreducible polynomial.  
   
   
       50 . A computer readable medium for a communications unit having circuitry operable to communicate using a superframe stored by the computer readable medium, the superframe comprising: 
 a first data unit including:    a header containing first header bits of a first payload signal and a first error check code representing a sum of the remainder of division of said first header bits by a generator polynomial and the remainder of division of hypothetical header bits by said generator polynomial, said hypothetical header bits greater in number than said first header bits; and    a payload field following said header for carrying said first payload signal; and    a second data unit including:    a header containing second header bits of a second payload signal equal in number to said first header bits and a second error check code representing the remainder of division of said second header bits by said generator polynomial; and    a payload field following the header for carrying said second payload signal.    
   
   
       51 . The computer readable medium of  claim 50 , wherein said hypothetical header bits comprise higher-significant bits of non-zero value and all-zero lower-significant bits equal in number to said first header bits plus the first error check code.  
   
   
       52 . The computer readable medium of  claim 51 , wherein said hypothetical header bits correspond in number to the maximum degree of an irreducible polynomial.