Patch substrate for external connection

Abstract

Embodiments include a generally planar patch substrate having external connection pads on one side, electrical connections connected to the external connection pads and extending through the substrate, and plated contacts formed on the electrical connections and extending beyond the other side of the patch substrate. The external connection pads may be connected to one electrical device using solder bumps or balls, and the plated contacts may be connected to contacts of another electrical device by thermo-compression bonding. Also, a surface of the patch substrate having the plated contacts may be attached to the other electrical device using an electrically insulating adhesive. Moreover, the plated contacts may have a smaller surface area than the external connection pads, so that the other electrical device can also have smaller contacts, leaving more space for electrically conductive traces to the contacts on the surface and within layers of the other electrical device.

1 . A method comprising: 
 forming a plurality of electrically conductive material columns in a plurality of via holes through a first surface of a generally planar patch substrate to a layer of foil on a second surface of the patch substrate, the columns having a plurality of exposed metal plates extending beyond the first surface; and    removing at least a portion of the layer of foil to form a plurality of external connection pads on the second surface, wherein the external connection pads have a contact surface area larger than a contact surface area of the exposed metal plates and are electronically connected to the exposed metal plates by the electrically conductive material columns.    
   
   
       2 . The method of  claim 1 , further comprising drilling the via holes through the generally planar patch substrate with a laser.  
   
   
       3 . The method of  claim 1 , wherein removing includes one of a print and etch process, a pattern and etch process, and a screen printed conductor process.  
   
   
       4 . A method comprising: 
 attaching a first side of a generally planar patch substrate to a surface of a first electronic device, the patch substrate including a second side disposed opposite from the first side, a plurality of external connection pads on the second side, a plurality of electrical connections coupled to the external connection pads and extending to the first side, and a plurality of metal plates on the electrical connections and extending beyond the first side, wherein attaching includes: 
 laminating the first surface of the patch substrate with an electrically insulating adhesive;  
 vacuum bonding the first side of to the surface of the first electronic device;  
 curing the electrically insulating adhesive;  
 thermo-compression bonding the metal plates to the first contacts.  
   
   
   
       5 . The method of  claim 4 , further comprising attaching the patch substrate to a second electronic device having a plurality of second contacts, wherein attaching comprises: 
 forming a plurality of solder balls or bumps on the plurality of external connection pads;    reflow interconnecting the solder balls or bumps to the second contacts.    
   
   
       6 . The method of  claim 4 , wherein first electronic device and second electronic device comprises a pair of one of a printed circuit board (PCB) and a packaging substrate, and a packaging substrate and printed circuit board (PCB).  
   
   
       7 . The method of  claim 4 , wherein the plurality of external connection pads have a contact surface area larger than a contact surface area of the exposed metal plates.  
   
   
       8 . The method of  claim 1 , wherein the columns are filed with electrically conductive material.  
   
   
       9 . The method of  claim 1 , wherein the via holes are filled with electrically conductive material.  
   
   
       10 . The method of  claim 1 , wherein the electrically conductive material comprises one of solder metallization, copper (Cu), silver, tin, aluminum, gold, and an organic solderability preservative (OSP).  
   
   
       11 . The method of  claim 4 , wherein the electrical connections comprise a plurality of columns filled with electrically conductive material.  
   
   
       12 . The method of  claim 4 , wherein the electrical connections comprise a plurality of via structures filled with electrically conductive material.  
   
   
       13 . The method of  claim 4 , wherein the electrical connections comprise a plurality of through holes filled with electrically conductive material.  
   
   
       14 . The method of  claim 11 , wherein the electrically conductive material comprises one of solder metallization, copper (Cu), silver, tin, aluminum, gold, and an organic solderability preservative (OSP).  
   
   
       15 . The method of  claim 12 , wherein the electrically conductive material comprises one of solder metallization, copper (Cu), silver, tin, aluminum, gold, and an organic solderability preservative (OSP).  
   
   
       16 . The method of  claim 13 , wherein the electrically conductive material comprises one of solder metallization, copper (Cu), silver, tin, aluminum, gold, and an organic solderability preservative (OSP).