Coding of FPGA and standard cell logic in a tiling structure

Abstract

A method and system for storing and modifying register transfer language (RTL) described logic types. Upon a declaration of a signal interconnect, a language extension of a register transfer language is defined for the signal interconnect based on the signal interconnect”s type. The language extensions allow different signal interconnect types, such as those used with field programmable gate arrays (FPGA) and standard cells, to be stored in a same file array hierarchy. This storage facilitates changing logic types, thus ultimately resulting in an integrated circuit (IC) that is either smaller (using more standard cells) or more flexible (using more FPGA cells). The transition from one RTL type to another is performed within the physical design cycle, in which wiring, timing and placement of components (information) is performed before masking out the final chip design.

1 - 21 . (canceled)  
   
   
       22 . An array of placeable logic tiles, said array comprising: 
 a plurality of placeable logic tiles, each of said plurality of placeable logic tiles having a same outline size by a different amount of field programmable gate array (FPGA) and standard cell logic, wherein a first placeable logic tile from said plurality can replace a second placeable logic tile from said plurality to effectively more a boundary between the FPGA and standard cell logic within the tile.    
   
   
       23 . A set of placeable logic tiles comprising: 
 a plurality of placeable logic tiles, each of said plurality of placeable logic tiles having a different outline size and a different amount of field programmable gate array (FPGA) and standard cell logic, wherein a first placeable logic tile can replace a second placeable logic tile of different outline size.