Apparatus and method for transaction tag mapping between bus domains

Abstract

An apparatus and method to provide tag mapping between bus domains across a bus bridge. The preferred embodiments provide a simple tag mapping design while maintaining unique IDs for all outstanding transactions for an overall increase in computer system performance. The preferred embodiment is a bus bridge between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and an output high speed interface (MPI bus). In preferred embodiments, the transaction mapping logic ensures that transactions generated by any logical unit (CPU) appear to originate from a single logical unit.

1 . A transaction tag mapping circuit in a computer bus bridge between a first transaction tag on a first bus and a second transaction tag on a second bus comprising: 
 logic to map transaction ID bits from the transaction tag on the first bus to transaction ID bits of a transaction tag on the second bus; and    logic to map at least one unit ID bit from the transaction tag on the first bus to the transaction ID bits of the transaction tag on the second bus to provide a unique transaction ID from the first bus to the second bus.    
   
   
       2 . The transaction tag mapping circuit of  claim 1  wherein the transaction tags on the first bus appear on the second bus to come from a single functional unit.  
   
   
       3 . The transaction tag mapping circuit of  claim 1  further comprising logic to map unit ID bits from the transaction tag on the first bus to the unit ID bits of the transaction tag on the second bus; and 
 logic to fill any unmapped unit ID bits in the transaction tag on the second bus with zeros.    
   
   
       4 . The transaction tag mapping circuit of  claim 3  further comprising logic to fill any node ID bits in the transaction tag on the second bus with zeros.  
   
   
       5 . The transaction tag mapping circuit of  claim 3  wherein the first bus is an API bus.  
   
   
       6 . The transaction tag mapping circuit of  claim 3  wherein the second bus is a MPI bus.  
   
   
       7 . The transaction tag mapping circuit of  claim 3  wherein the first bus is an API bus the second bus is a MPI bus and wherein: 
 five bits of the API transaction ID and one bit of the API unit ID are mapped to the MPI transaction ID;    4 bits of the API unit ID are mapped to the MPI unit ID and a remaining bit of the MPI unit ID is set to zero; and    the node ID bits of the MPI transaction tag are set to zero.    
   
   
       8 . The transaction tag mapping circuit of  claim 1  wherein the first bus is an API bus.  
   
   
       9 . The transaction tag mapping circuit of  claim 1  wherein the second bus is a MPI bus.  
   
   
       10 . A computer system with a transaction tag mapping circuit in a bus bridge between a first computer system bus and a second computer system bus comprising: 
 logic to map transaction ID bits from the transaction tag on the first computer system bus to the transaction ID bits of a transaction tag on the second computer system bus;    logic to map at least one unit ID bit from the transaction tag on the first computer system bus to the transaction ID bits of a transaction tag on the second computer system bus;    logic to map unit ID bits from the transaction tag on the first computer system bus to the unit ID bits of a transaction tag on the second computer system bus; and    logic to fill any unmapped unit ID bits in the transaction tag on the second computer system bus with zeros.    
   
   
       11 . The computer system of  claim 10  further comprising logic to fill any node ID bits in the transaction tag on the second computer system bus with zeros  
   
   
       12 . The computer system of  claim 10  wherein the transaction tags on the first bus appear on the second bus to come from a single functional unit.  
   
   
       13 . The computer system of  claim 10  wherein the first bus is an API bus.  
   
   
       14 . The computer system of  claim 10  wherein the first bus is a MPI bus.  
   
   
       15 . The computer system of  claim 10  wherein the first bus is an API bus the second bus is a MPI bus and wherein: 
 five bits of the API transaction ID and one bit of the API unit ID are mapped to the MPI transaction ID;    4 bits of the API unit ID are mapped to the MPI unit ID and a remaining bit of the MPI unit ID is set to zero; and    the node ID bits of the MPI transaction tag are set to zero.    
   
   
       16 . A method for mapping transaction tags between a transaction tag of a first bus having a transaction ID field and a unit ID field and a transaction tag of a second bus having a transaction ID field, and a unit ID field, the method comprising the steps of: 
 mapping transaction ID bits from the first bus transaction tag to transaction tag ID bits of the second bus transaction tag;    filling a remainder of the transaction ID field of the second bus with unit ID bits from the transaction tag of the first bus;    mapping the remainder of the unit ID bits from the first bus transaction tag to the unit ID bits in the second bus; and    placing zeros in any remaining bits of the unit ID bits in the second bus transaction tag.    
   
   
       17 . The method of  claim 15  wherein the transaction tag of the second bus further comprises a node ID field and the method further comprises the step of placing zeros in the node ID bits in the second bus transaction tag.  
   
   
       18 . The method of  claim 15  wherein the first bus is an API bus.  
   
   
       19 . The method of  claim 15  wherein the second bus is a MPI bus.  
   
   
       20 . The method of  claim 15  wherein the transaction tags on the first bus appear on the second bus to come from a single functional unit.