Semiconductor device having a merged region and method of fabrication

Abstract

A semiconductor device includes an insulated gate electrode pattern formed on a well region. The semiconductor device further includes a sidewall spacer formed on sidewalls of the gate electrode pattern. A source region and a drain region are formed adjacent opposite sides of the gate pattern. In accordance with one embodiment of the present invention, one of the source or drain regions includes a first-concentration impurity region formed under the sidewall spacer. The semiconductor device further includes a silicide layer formed within the well region wherein at least a part of the silicide layer contacts a portion of the well region to bias the well region. A method of manufacturing the semiconductor device is also provided.

1 . A method for forming a semiconductor device, the method comprising: 
 forming an insulated gate electrode pattern on a well region;    forming a first-concentration impurity region adjacent first and second sides of the gate pattern, the first side being opposite to the second side;    forming a sidewall spacer on sidewalls of the gate pattern;    covering the first side of the gate pattern with a mask, and ion implanting impurities into the resulting structure to form a second-concentration impurity region under the second side of the gate pattern adjacent the sidewall spacer; and    forming a silicide layer within the well region adjacent the first side of the gate pattern, wherein at least a part of the silicide layer adjacent the first side of the gate pattern contacts a portion of the well region to bias the well region;    
   
   
       2 . The method of  claim 1 , wherein the silicide layer is formed on the first-concentration impurity region.  
   
   
       3 . The method of  claim 1 , further comprising: 
 forming a silicide layer adjacent the sidewall spacer of the second side of the gate pattern, wherein the silicide layer does not contact any portion of the well region.    
   
   
       4 . The method of  claim 1 , further comprising forming a silicide layer on the gate electrode pattern.  
   
   
       5 . A method for forming a semiconductor device, the method comprising: 
 forming an insulated gate electrode pattern on a well region;    forming a first-concentration impurity region adjacent first and second sides of the gate pattern, the first side being opposite to the second side;    forming a sidewall spacer on sidewalls of the gate pattern;    ion implanting impurities into the resulting structure to form a second-concentration impurity region under the second side of the gate pattern adjacent the sidewall spacer; and    forming a silicide layer within the well region adjacent the sidewall spacer,    wherein at least a part of the silicide layer adjacent the first side of the gate pattern contacts a portion of the well region to bias the well region;    
   
   
       6 . The method of  claim 5 , wherein the silicide layer is formed on the first-concentration impurity region.  
   
   
       7 . The method of  claim 5 , further comprising forming a silicide layer on the gate electrode pattern.  
   
   
       8 . A semiconductor device comprising: 
 a first transistor and a second transistor having an isolation region disposed therebetween, the first and second transistors respectively formed on first and second well regions, the first transistor including:    a first insulated gate electrode pattern formed on the first well region of a first-conductivity type,    a first sidewall spacer formed on sidewalls of the first gate pattern,    a first source region and a first drain region of a second-conductivity type formed adjacent opposite sides of the first gate pattern, the first source region including:    a first-concentration impurity region of a second conductivity type formed under the first sidewall spacer, and a first silicide layer formed within the first well region,    wherein at least a part of the first silicide layer contacts a portion of the first well region for biasing the first well region; and    the second transistor including:    a second insulated gate electrode pattern formed on the second well region of a second-conductivity type,    a second sidewall spacer formed on sidewalls of the second gate pattern;    a second source region and a drain region of a first-conductivity type formed adjacent opposite sides of the second gate pattern, the second source region including:    a second first-concentration impurity region of a first conductivity type formed under the second sidewall spacer, and    a second silicide layer formed within the second well region,    wherein at least a part of the second silicide layer contacts a portion of the second well region for biasing the second well region.    
   
   
       9 . The semiconductor device of  claim 8 , wherein the first-conductivity type is p-type and the second-conductivity type is n-type.  
   
   
       10 . The semiconductor device of  claim 9 , further comprising a ground line electrically connected to the first well region and the first source region through the first silicide layer and a power supply line electrically connected to the second well region and the second source region through the second silicide layer.  
   
   
       11 . The semiconductor device of  claim 8 , wherein the first-conductivity type is n-type and the second-conductivity type is p-type.  
   
   
       12 . The semiconductor device of  claim 11 , further comprising a ground line electrically connected to the second well region and the second source region through the second silicide layer and a power supply line electrically connected to the first well region and the first source region through the first silicide layer.  
   
   
       13 . The semiconductor device of  claim 8 , further comprising silicide layers in the drain regions in the first well region and second well region, wherein the silicide layers do not contact any portion of the first and second well regions.  
   
   
       14 . The semiconductor device of  claim 8 , further comprising silicide layers formed on the first and second gate electrode patterns.  
   
   
       15 . The semiconductor device of  claim 8 , wherein the first silicide layer is formed within and on the first-concentration impurity region,  
   
   
       16 . The semiconductor device of  claim 8 , wherein the second silicide layer is formed within and on the second first-concentration impurity region