Method for producing an electronic component with shielding

Abstract

An electronic component with shielding is described. The component has a semiconductor chip with a semiconductor substrate. Disposed in a region of a rear side of the semiconductor substrate is an electrically conductive buried layer. The buried layer is connected via a ground lead, disposed within the semiconductor substrate, to a contact area and an external ground potential. Furthermore, the invention relates to a method for producing an electronic component of this type.

1 . A method for producing an electronic component with shielding, which comprises the steps of: 
 providing a semiconductor wafer functioning as a semiconductor substrate formed of a semiconductor material and having an active upper side for at least one integrated circuit and a passive rear side;    implanting impurities from the passive rear side of the semiconductor wafer for forming a buried layer being electrically conductive and having a surface area corresponding in size to a surface area of the passive rear side of the semiconductor substrate;    introducing an electrically conductive annular layer from the active upper side of the semiconductor wafer as far as the buried layer in an edge region of the integrated circuit;    producing the integrated circuit within the electrically conductive annular layer in the semiconductor substrate defining a semiconductor chip; and    packaging the semiconductor chip to form the electronic component with the shielding.    
   
   
       2 . The method according to  claim 1 , which comprises doping the semiconductor material with an impurity concentration of at least 1×10 20  cm −3  for producing the buried layer.  
   
   
       3 . The method according to  claim 2 , which comprises forming and soldering solder formations selected from the group consisting of solder balls and solder contact bumps onto contact areas on the active upper side of the semiconductor wafer.  
   
   
       4 . The method according to  claim 3 , which comprises connecting the solder formations to a support selected from the group consisting of a printed-circuit board and a ceramic substrate, and connecting at the same time at least one of the solder formations to a ground potential terminal.  
   
   
       5 . The method according to  claim 3 , which comprises connecting the contact areas to connecting lines of a wiring foil having further solder formations selected from the group consisting of solder balls and solder contact bumps.  
   
   
       6 . The method according to  claim 5 , which comprises connecting the further solder formations of the wiring foil to lines of a support selected from the group consisting of a printed-circuit board and of a ceramic substrate, at least one of the further solder formations being connected to a ground-carrying line of the support.  
   
   
       7 . The method according to  claim 1 , which comprises disposing an annular contact area, which establishes electrical contact with the electrically conductive annular layer, in an edge region of the upper side of the semiconductor chip.  
   
   
       8 . The method according to  claim 6 , which comprises electrically connecting one of a number of annularly disposed solder balls and a number of annularly disposed solder contact bumps to the electrically conductive annular layer in an edge region of the individual semiconductor chip.  
   
   
       9 . A method for producing an electronic component with shielding, which comprises the following steps: 
 providing a semiconductor wafer functioning as a semiconductor substrate having an active upper side for at least one integrated component and a passive rear side;    growing an electrically conductive layer formed of an electrically conductive semiconductor material and thereafter an electrically intrinsically conductive layer formed of an electrically intrinsic conductive semiconductor material on the active upper side of the semiconductor wafer by epitaxial growth, the electrically conductive layer becoming a buried layer adjacent the electrically intrinsically conductive layer;    introducing an electrically conductive annular layer from the active upper side of the semiconductor wafer, the electrically conductive annular layer extending through the electrically intrinsically conductive layer as far as the buried layer, the electrically conductive annular layer disposed in an edge region of the semiconductor substrate;    producing the integrated circuit within the electrically conductive annular layer in the semiconductor substrate defining a semiconductor chip; and    packaging the individual conductor chips to form the electronic component with the shielding.    
   
   
       10 . The method according to  claim 9 , which comprises doping the semiconductor material with an impurity concentration of at least 1×10 20  cm −3  for forming the buried layer.  
   
   
       11 . The method according to  claim 10 , which comprises forming and soldering solder formations selected from the group consisting of solder balls and solder contact bumps onto contact areas on the active upper side of the semiconductor wafer.  
   
   
       12 . The method according to  claim 11 , which comprises connecting the solder formations to a support selected from the group consisting of a printed-circuit board and a ceramic substrate, and connecting at the same time at least one of the solder formations to a ground potential terminal.  
   
   
       13 . The method according to  claim 11 , which comprises connecting the contact areas to connecting lines of a wiring foil, the wiring foil having further solder formations selected from the group consisting of solder balls and solder contact bumps.  
   
   
       14 . The method according to  claim 13 , which comprises connecting the further solder formations of the wiring foil to lines of a support selected from the group consisting of a printed-circuit board and of a ceramic substrate, at least one of the further solder formations being connected to a ground-carrying line of the support.  
   
   
       15 . The method according to  claim 9 , which comprises disposing an annular contact area, which establishes electrical contact for the electrically conductive annular layer, in an edge region of the upper side of the semiconductor chip.  
   
   
       16 . The method according to  claim 15 , which comprises electrically connecting one of a number of annularly disposed solder balls and a number of annularly disposed solder contact bumps to the electrically conductive annular layer in an edge region of the semiconductor chip.