Method and system for mobile multimedia processor supporting rate adaptation and mode selection

Abstract

Aspects for a method and system for a mobile multimedia processor supporting rate adaptation and mode selection are provided. A method for a mobile multimedia processor supporting rate adaptation and mode selection may comprise latching a received address signal at a received clock rate via a received write enable signal. The received clock rate may be converted to a latched clock rate, and a latched address signal may be generated at the latched clock rate via a latched write enable signal. A system for a mobile multimedia processor supporting rate adaptation and mode selection may comprise circuitry that latches a received address signal at a received clock rate via a received write enable signal. The received clock rate may be converted, by the circuitry, to a latched clock rate. A latched address signal may be generated at the latched clock rate via a latched write enable signal.

1 . A method for generating an address in a mobile multimedia processor, the method comprising: 
 latching, in a mobile multimedia processor, a received address signal, received at a received clock rate, via a received write enable signal;    converting, in said mobile multimedia processor, said received clock rate to a latched clock rate; and    generating, in said mobile multimedia processor, and at said latched clock rate, a latched address signal corresponding to said received address signal, via a latched write enable signal.    
   
   
       2 . The method according to  claim 1 , wherein said received clock rate comprises a higher clock rate than said latched clock rate.  
   
   
       3 . The method according to  claim 1 , further comprising latching a current binary value of said received address signal at a current time instant based on a corresponding current binary value of said received write enable signal.  
   
   
       4 . The method according to  claim 3 , further comprising generating a current binary value of said latched address signal based on said current binary value of said received address signal.  
   
   
       5 . The method according to  claim 4 , further comprising maintaining said current binary value of said latched address signal for a time duration based on a corresponding current binary value of said latched write enable signal.  
   
   
       6 . The method according to  claim 1  further comprising detecting a change in a current binary value of said received write enable signal at a current instant in time.  
   
   
       7 . The method according to  claim 6 , further comprising generating a change in a corresponding current binary value of said latched write enable signal based on said detected change in said current binary value of said received write enable signal.  
   
   
       8 . The method according to  claim 7 , further comprising maintaining a subsequent value of said latched write enable signal, generated based on said generated change in said corresponding current binary value of said latched write enable signal, for a time duration based on said latched clock rate.  
   
   
       9 . The method according to  claim 8 , further comprising generating a subsequent change in said subsequent value of said latched write enable signal at a time instant subsequent to an end of said time duration based on said latched clock rate in response to a subsequent change in said received write enable signal.  
   
   
       10 . The method according to  claim 1 , further comprising selecting one of: said received address signal, and said latched address signal, based on a mode signal.  
   
   
       11 . The method according to  claim 10 , further comprising communicating said selected one of: said received address signal, and said latched address signal, to external circuitry.  
   
   
       12 . A system for generating an address in a mobile multimedia processor, the system comprising: 
 circuitry that latches, in a mobile multimedia processor, a received address signal, received at a received clock rate, via a received write enable signal;    said circuitry converts, in said mobile multimedia processor, said received clock rate to a latched clock rate; and    said circuitry generates, in said mobile multimedia processor, and at said latched clock rate, a latched address signal corresponding to said received address signal, via a latched write enable signal.    
   
   
       13 . The system according to  claim 12 , wherein said received clock rate comprises a higher clock rate than said latched clock rate.  
   
   
       14 . The system according to  claim 12 , wherein said circuitry latches a current binary value of said received address signal at a current time instant based on a corresponding current binary value of said received write enable signal.  
   
   
       15 . The system according to  claim 14 , wherein said circuitry generates a current binary value of said latched address signal based on said current binary value of said received address signal.  
   
   
       16 . The system according to  claim 15 , wherein said circuitry maintains said current binary value of said latched address signal for a time duration based on a corresponding current binary value of said latched write enable signal.  
   
   
       17 . The system according to  claim 12  wherein said circuitry detects a change in a current binary value of said received write enable signal at a current instant in time.  
   
   
       18 . The system according to  claim 17 , wherein said circuitry generates a change in a corresponding current binary value of said latched write enable signal based on said detected change in said current binary value of said received write enable signal.  
   
   
       19 . The system according to  claim 18 , wherein said circuitry maintains a subsequent value of said latched write enable signal, generated based on said generated change in said corresponding current binary value of said latched write enable signal, for a time duration based on said latched clock rate.  
   
   
       20 . The system according to  claim 19 , wherein said circuitry generates a subsequent change in said subsequent value of said latched write enable signal at a time instant subsequent to an end of said time duration based on said latched clock rate in response to a subsequent change in said received write enable signal.  
   
   
       21 . The system according to  claim 12 , wherein said circuitry selects one of: said received address signal, and said latched address signal, based on a mode signal.  
   
   
       22 . The system according to  claim 21 , wherein said circuitry communicates said selected one of: said received address signal, and said latched address signal, to external circuitry.