Perimeter matrix ball grid array circuit package with a populated center

Abstract

A ball grid array (BGA) integrated circuit package which has an outer two-dimensional array of solder balls and a center two-dimensional array of solder balls located on a bottom surface of a package substrate. The solder balls are typically reflowed to mount the package to a printed circuit board. Mounted to an opposite surface of the substrate is an integrated circuit that is electrically coupled to the solder balls by internal routing within the package. The outer array of solder balls are located the dimensional profile of the integrated circuit to reduce solder stresses induced by the differential thermal expansion between the integrated circuit and the substrate. The center solder balls are typically routed directly to ground and power pads of the package to provide a direct thermal and electrical path from the integrated circuit to the printed circuit board.

1 - 16 . (canceled)  
   
   
       2 . A semiconductor package, comprising: 
 a substrate that includes a top surface and an exposed external opposite surface including an inner region, an outer region, and a middle region that separates the inner and outer regions;    a plurality of contracts including a first plurality of contacts and a second plurality of contacts, said first plurality of contacts located in the outer region, and said second plurality of contacts located in the inner region, wherein the middle region is free of contacts over a distance that is larger than the smallest distances between adjacent contacts in the inner and outer regions; and    an integrated circuit that is mounted to said top surface of said substrate, wherein said first and second plurality of contacts are located respectively outside and inside a dimensional profile of said integrated circuit.    
   
   
       18 . The semiconductor package of claim  17 , wherein the distances between adjacent contacts in the inner region are equal to the distances between adjacent contacts in the outer region.  
   
   
       19 . The semiconductor package of claim  17 , further comprising a plurality of electrically conductive members attached to said plurality of contacts of said first and second plurality of contacts.  
   
   
       20 . The semiconductor package of claim  17 , wherein said top surface of said substrate has a ground bus that is coupled to said integrated circuit and connected to said second plurality of contacts by a plurality of vias that extend through said substrate.  
   
   
       21 . The semiconductor package of claim  17 , wherein said top surface of said substrate has a power bus that is coupled to said integrated circuit and connected to said second plurality of contacts by a plurality of vias that extend through said substrate.  
   
   
       22 . The semiconductor package of claim  17 , further comprising an encapsulant enclosing said integrated circuit.