US2006176722A1PendingUtilityA1

Method of operating a content addressable memory with reduced instantaneous current and power consumption during a search

36
Individually held — no corporate assignee on recordPriority: Oct 12, 2004Filed: Jan 17, 2006Published: Aug 10, 2006
Est. expiryOct 12, 2024(expired)· nominal 20-yr term from priority
Inventors:Paul B. RipyGary GeerdesPaul O'ConnorChristophe Leroy
G11C 15/04
36
PatentIndex Score
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Claims

Abstract

The power required to search a content addressable memory (CAM) is substantially reduced by forming the CAM to have a number of CAM banks with a corresponding number of power switches that control power to the CAM banks, and then controlling the power to search the CAM banks one at a time.

Claims

exact text as granted — not AI-modified
1 - 10 . (canceled)  
   
   
       11 . A method of operating a content addressable memory (CAM), the method comprising: 
 generating a pointer;    storing entries in the CAM when the CAM is not full;    changing the pointer by one when an entry is stored.    
   
   
       12 . The method of  claim 11  wherein: 
 the CAM has two or more CAM banks, each CAM bank has a plurality addresses,    the pointer is a last address pointer identifying an address of a last valid entry in a sequence of entries,    entries are stored in the CAM in a sequential manner, each entry is stored in the CAM at an address that is next in sequence after the address identified by the last address pointer, and    the last address pointer is changed so that the last address pointer points to the address of where the last entry was stored.    
   
   
       13 . The method of  claim 12  and further comprising: 
 determining if the CAM is full; and    outputting a CAM full status signal when the CAM is full.    
   
   
       14 . The method of  claim 12  and further comprising: 
 determining if the address identified by the last address pointer is at a CAM bank boundary; and    changing the CAM bank pointer by one when the address identified by the last address pointer is at the CAM bank boundary.    
   
   
       15 . The method of  claim 12  and further comprising: 
 searching a first CAM bank and, after a search period, determining if a match was found;    when a match is found, setting the first signal to indicate that a match was found, and the second signal to include an address of where the match is located; and    when no match is found, searching a next CAM bank.    
   
   
       16 . The method of  claim 15  wherein, when no match is found: 
 determining if a CAM bank counter value is equal to a maximum CAM bank counter value; and    increasing the CAM bank counter value by one when the CAM bank counter value is not equal to the maximum before the next CAM bank is searched.    
   
   
       17 . The method of  claim 15  and further comprising: 
 searching the CAM banks to identify an entry address of an entry to be deleted;    deleting the entry at the entry address;    determining if the entry address and the address identified by the last address pointer are a same address; and    changing the last address pointer when the entry address and the address identified by the last address pointer are the same address.    
   
   
       18 . The method of  claim 17  and further comprising: 
 storing an entry at the address identified by the last address pointer at the entry address after deletion when the entry address and the address identified by the last address pointer are not a same address; and    changing the last address pointer when the entry address and the address identified by the last address pointer are not the same address.    
   
   
       19 - 20 . (canceled)  
   
   
       21 . A method of operating a content addressable memory (CAM), the method comprising: 
 simultaneously outputting a comparand to two or more cell arrays of the CAM, each cell array having rows and columns of CAM cells;    searching only a first cell array of the two or more cell arrays to determine if the comparand is stored in the first cell array, the first cell array indicating when a data value stored in any row in the first cell array matches the comparand.    
   
   
       22 . The method of  claim 21  and further comprising searching only a second cell array of the two or more cell arrays to determine if the comparand is stored in the second cell array when the comparand is not stored in the first cell array, the second cell array indicating when a data value stored in any row in the second cell array matches the comparand.  
   
   
       23 . The method of  claim 22  wherein the first cell array indicates where the data value in the first cell array is located, and the second cell array indicates where the data value in the second cell array is located.  
   
   
       24 . The method of  claim 22  and further comprising outputting a master signal when any of the two or more cell arrays indicate that a match has been found.  
   
   
       25 . The method of  claim 22  wherein searching includes sequentially applying search power to the two or more cell arrays so that only one cell array can be searched at a time to indicate if a data value matches the comparand.  
   
   
       26 - 30 . (canceled)  
   
   
       31 . A method of operating a content addressable memory (CAM), the method comprising: 
 simultaneously outputting a comparand to two or more cell arrays of the CAM, each cell array having a hit line, rows and columns of CAM cells, and rows of match lines such that each row of CAM cells has a corresponding match line; and    placing a voltage on the match lines of only a first cell array of the two or more cell arrays to determine if the comparand is stored in the first cell array, a voltage on the hit line of the first cell array having a first logic state when a data value stored in the first cell array matches the comparand, and a second logic state when no data value matches the comparand.    
   
   
       32 . The method of  claim 31  and further comprising placing the voltage on the match lines of only a second cell array of the two or more cell arrays to determine if the comparand is stored in the second cell array when the comparand is not stored in the first cell array, a voltage on the hit line of the second cell array having the first logic state when a data value stored in the second cell array matches the comparand, and the second logic state when no data value matches the comparand.  
   
   
       33 . The method of  claim 32  and further comprising outputting first index information that indicates where the data value is located in the first cell array when the hit signal of the first cell array has the first logic state, and second index information that indicates where the data value is located in the second cell array when the hit signal of the second cell array has the first logic state.  
   
   
       34 . The method of  claim 32  and further comprising: 
 detecting a logic state on each hit line; and    outputting a master signal when the logic state on any hit line indicates that a match has been found.    
   
   
       35 . The method of  claim 32  wherein the voltage is only placed on the match lines of one cell array at a time.  
   
   
       36 - 40 . (canceled)  
   
   
       41 . The method of  claim 25  wherein a row of cells in a cell array stores a number of bits of data, and the comparand has an equivalent number of bits of data.  
   
   
       42 . The method of  claim 25  wherein a row of cells in a cell array stores a number of bits of data, and the comparand has a smaller number of bits of data.  
   
   
       43 . The method of  claim 22  wherein no more cell arrays are searched when a cell array indicates that a data value matches the comparand.  
   
   
       44 . The method of  claim 22  wherein each cell array is searched even if a cell array indicates that a data value matches the comparand.  
   
   
       45 . The method of  claim 22  wherein two or more word lines are connected to the two or more cell arrays so that each word line is connected to each cell array.  
   
   
       46 . The method of  claim 32  wherein a row of cells in a CAM array stores a number of bits of data, and the comparand has an equivalent number of bits of data.  
   
   
       47 . The CAM of  claim 32  wherein a row of cells in a CAM array stores a number of bits of data, and the comparand has a smaller number of bits of data.  
   
   
       48 . The method of  claim 32  wherein the voltage is placed on the match lines of no more cell arrays when the hit signal of a cell array has the first logic state.  
   
   
       49 . The method of  claim 32  wherein the voltage is placed on the match lines of each cell array even if the hit signal of a cell array has the first logic state.  
   
   
       50 . The method of  claim 32  wherein two or more word lines are connected to the two or more cell arrays so that each word line is connected to each cell array.

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