Delay locked loop circuit

Abstract

A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.

1 . A delay locked loop circuit, comprising: 
 a delay element for generating a delayed clock signal which transitions from a first logic level to a second logic level with a delay from a first transition of a reference clock signal from a first logic level to a second logic level;    a signal generation circuit for generating first and second signals which complementarily change according to the first transition of the reference clock signal, a second transition of the reference clock signal from the second logic level to the first logic level, and a transition of the delayed clock signal;    a charge pump circuit for performing, according to the first and second signals, a first operation during an interval extending from the first transition of the reference clock signal to the transition of the delayed clock signal and a second operation during an interval extending from the transition of the delayed clock signal to the second transition of the reference clock signal, the first operation being any one of a push operation and a pull operation, and the second operation being the other of the push operation and the pull operation; and    a loop filter which receives an output of the charge pump circuit,    wherein the delay element controls a delay amount between the first transition of the reference clock signal and the transition of the delayed clock signal based on an output of the loop filter.    
   
   
       2 . The delay locked loop circuit of  claim 1 , wherein: 
 the first signal generated by the signal generation circuit is at a first logic level during the interval extending from the first transition of the reference clock signal to the transition of the delayed clock signal but otherwise at a second logic level, and the second signal generated by the signal generation circuit is at a first logic level during the interval extending from the transition of the delayed clock signal to the second transition of the reference clock signal but otherwise at a second logic level;    the charge pump circuit includes 
 a first current source for supplying a first current relevant to the first operation,  
 a second current source for supplying a second current relevant to the second operation,  
 a first switch which conducts the first current when the first signal is at the first logic level but interrupts the first current when the first signal is at the second logic level, and  
 a second switch which conducts the second current when the second signal is at the first logic level but interrupts the second current when the second signal is at the second logic level; and  
   the delay element decreases the delay amount according to any one of an increase and decrease in an output voltage of the loop filter but increases the delay amount according to the other of the increase and decrease.    
   
   
       3 . The delay locked loop circuit of  claim 2 , wherein the first current and the second current have the same magnitude.  
   
   
       4 . The delay locked loop circuit of  claim 1 , wherein: 
 the first signal generated by the signal generation circuit is at a first logic level during the interval extending from the first transition of the reference clock signal to the transition of the delayed clock signal but otherwise at a second logic level, and the second signal generated by the signal generation circuit is at a first logic level during the interval extending from the first transition to second transition of the reference clock signal but otherwise at a second logic level;    the charge pump circuit includes 
 a first current source for supplying a first current relevant to the first operation,  
 a second current source for supplying a second current relevant to the second operation,  
 a first switch which conducts the first current when the first signal is at the first logic level but interrupts the first current when the first signal is at the second logic level, and  
 a second switch which conducts the second current when the second signal is at the first logic level but interrupts the second current when the second signal is at the second logic level; and  
   the delay element decreases the delay amount according to any one of an increase and decrease in an output voltage of the loop filter but increases the delay amount according to the other of the increase and decrease.    
   
   
       5 . The delay locked loop circuit of  claim 4 , wherein the magnitude of the first current is twice that of the second current.  
   
   
       6 . The delay locked loop circuit of  claim 1 , wherein: 
 the first signal generated by the signal generation circuit is at a first logic level during the interval extending from the first transition of the reference clock signal to the transition of the delayed clock signal but otherwise at a second logic level, and the second signal generated by the signal generation circuit is at a first logic level during the interval extending from the first transition to second transition of the reference clock signal but otherwise at a second logic level;    the charge pump circuit includes 
 first and fourth current sources for respectively supplying first and fourth currents relevant to the first operation,  
 second and third current sources for respectively supplying second and third currents relevant to the second operation,  
 a first switch which conducts the first current when the first signal is at the first logic level but interrupts the first current when the first signal is at the second logic level,  
 a second switch which conducts the second current when the second signal is at the first logic level but interrupts the second current when the second signal is at the second logic level,  
 a third switch which interrupts the third current when the first signal is at the first logic level but conducts the third current when the first signal is at the second logic level, and  
 a fourth switch which interrupts the fourth current when the second signal is at the first logic level but conducts the fourth current when the second signal is at the second logic level; and  
   the delay element decreases the delay amount according to any one of an increase and decrease in an output voltage of the loop filter but increases the delay amount according to the other of the increase and decrease.    
   
   
       7 . The delay locked loop circuit of  claim 6 , wherein: 
 the second, third and fourth currents have the same magnitude; and    the magnitude of the first current is three times that of each of the second, third and fourth currents.    
   
   
       8 . The delay locked loop circuit of  claim 1 , wherein: 
 the first signal generated by the signal generation circuit is at a first logic level during the interval extending from the first transition of the reference clock signal to the transition of the delayed clock signal but otherwise at a second logic level, and the second signal generated by the signal generation circuit is at a first logic level during the interval extending from the first transition to second transition of the reference clock signal but otherwise at a second logic level;    the charge pump circuit includes 
 first, fourth and fifth current sources for respectively supplying first, fourth and fifth currents relevant to the first operation,  
 second and third current sources for respectively supplying second and third currents relevant to the second operation,  
 a first switch which conducts the first current when the first signal is at the first logic level but interrupts the first current when the first signal is at the second logic level,  
 a second switch which conducts the second current when the second signal is at the first logic level but interrupts the second current when the second signal is at the second logic level,  
 a third switch which interrupts the third current when the first signal is at the first logic level but conducts the third current when the first signal is at the second logic level, and  
 a fourth switch which interrupts the fourth current when the second signal is at the first logic level but conducts the fourth current when the second signal is at the second logic level; and  
   the delay element decreases the delay amount according to any one of an increase and decrease in an output voltage of the loop filter but increases the delay amount according to the other of the increase and decrease.    
   
   
       9 . The delay locked loop circuit of  claim 8 , wherein: 
 the first current and the third current have the same magnitude;    the second, fourth and fifth currents have the same magnitude; and    the magnitude of each of the first and third currents is twice that of each of the second, fourth and fifth currents.    
   
   
       10 . The delay locked loop circuit of  claim 1 , wherein: 
 the first signal generated by the signal generation circuit is at a first voltage during the interval extending from the first transition of the reference clock signal to the transition of the delayed clock signal but otherwise at a second voltage, and the second signal generated by the signal generation circuit is at the second voltage during the interval extending from the first transition to second transition of the reference clock signal but otherwise at the first voltage;    the charge pump circuit includes 
 a first resistance which receives the first signal,  
 a second resistance which receives the second signal, and  
 a third resistance, one end of which is connected to a connection point of the first and second resistances, the other end being supplied with a third voltage;  
   the loop filter includes 
 a capacitance, and  
 an operational amplifier, a negative feedback portion of which is connected to the capacitance, an inversion input terminal of the operational amplifier being connected to a connection point of the first, second and third resistances of the charge pump circuit, and a non-inverted input terminal of the operational amplifier being supplied with a fourth voltage; and  
   the delay element decreases the delay amount according to any one of an increase and decrease in an output voltage of the operational amplifier of the loop filter but increases the delay amount according to the other of the increase and decrease.    
   
   
       11 . The delay locked loop circuit of  claim 10 , wherein: 
 the second voltage is equal to the third voltage;    the fourth voltage is at a midlevel between the first voltage and the second voltage;    the second resistance and the third resistance have the same resistance value; and    a resistance value of the first resistance is a half of that of each of the second and third resistances.    
   
   
       12 . The delay locked loop circuit of  claim 1 , wherein the delay element includes: 
 a first circuit including first and second transistors connected in series which have opposite polarities and receive the reference clock signal at their gates and a third transistor connected between the first and second transistors which receives an output of the loop filter at its gate; a voltage of a predetermined node between the first and second transistors being output from the first circuit as an output signal;    a second circuit for shaping a waveform of the output signal of the first circuit.    
   
   
       13 . The delay locked loop circuit of  claim 12 , wherein the first circuit includes a current source connected in parallel with the third transistor.  
   
   
       14 . The delay locked loop circuit of  claim 12 , wherein the second circuit includes: 
 an inverter which receives the output signal of the first circuit; and    a transistor which receives an input and output of the inverter at a drain and gate, respectively, a predetermined voltage being applied to the source of the transistor.    
   
   
       15 . The delay locked loop circuit of  claim 1 , wherein the delay amount of the delay element is gradually increased to lock a delay which extends from the first transition of the reference clock signal to the transition of the delayed clock signal.  
   
   
       16 . A delay locked loop circuit, comprising: 
 first and second delay locked loop circuits, each of which is the delay locked loop circuit of  claim 1 , the first and second delay locked loop circuits being supplied with a common reference clock signal; and    a clock generation circuit for generating a delayed clock signal from clock signals output from the first and second delay locked loop circuits, the delayed clock signal including any one of a rising edge and a falling edge with a delay from a rising of the common reference clock signal and including the other edge with a delay from a falling of the common reference clock signal.    
   
   
       17 . The delay locked loop circuit of  claim 16 , wherein: 
 the first delay locked loop circuit outputs a clock signal whose logic level transitions with a delay from a rising of the common reference clock signal, the delay being equal to a half of an on-duty period of the common reference clock signal; and    the second delay locked loop circuit outputs a clock signal whose logic level transitions with a delay from a falling of the common reference clock signal, the delay being equal to a half of an off-duty period of the common reference clock signal.    
   
   
       18 . A delay locked loop circuit, comprising: 
 a first delay locked loop circuit which is the delay locked loop circuit of  claim 1 , the first delay locked loop circuit being supplied with a first reference clock signal;    a second delay locked loop circuit which is the delay locked loop circuit of  claim 1 , the second delay locked loop circuit being supplied with a second reference clock signal which is in a phase opposite to that of the first reference clock signal; and    a clock generation circuit for generating a delayed clock signal from clock signals output from the first and second delay locked loop circuits, the delayed clock signal including any one of a rising edge and a falling edge with a delay from a rising of the first reference clock signal and including the other edge with a delay from a falling of the first reference clock signal.    
   
   
       19 . The delay locked loop circuit of  claim 18 , wherein: 
 the first delay locked loop circuit outputs a clock signal whose logic level transitions with a delay from a rising of the first reference clock signal, the delay being equal to a half of an on-duty period of the first reference clock signal; and    the second delay locked loop circuit outputs a clock signal whose logic level transitions with a delay from a rising of the second reference clock signal, the delay being equal to a half of an on-duty period of the second reference clock signal.