Random access memory with post-amble data strobe signal noise rejection

Abstract

A random access memory includes a control circuit configured to receive a strobe signal and generate a pulse after one edge of the strobe signal and before the next edge of the strobe signal for each cycle of a clock signal and a latch circuit configured to receive the strobe signal and the pulse. The latch circuit is configured to latch data signals into the latch circuit with the strobe signal and to receive the pulse to prevent post-amble noise on the strobe signal from latching other signals into the latch circuit.

1 - 8 . (canceled)  
     
     
         9 . A random access memory comprising: 
 a control circuit configured to receive a strobe signal and generate a pulse after one edge of the strobe signal and before the next edge of the strobe signal for each cycle of a clock signal, and    a latch circuit configured to receive the strobe signal and the pulse, wherein the latch circuit is configured to latch data signals into the latch circuit with the strobe signal and to receive the pulse to prevent post-amble noise on the strobe signal from latching other signals into the latch circuit.    
     
     
         10 . (canceled)  
     
     
         11 . The random access memory of  claim 9 , wherein the control circuit comprises a delay chain configured to receive the clock signal.  
     
     
         12 . The random access memory of  claim 11 , wherein the control circuit comprises a logic circuit configured to receive the strobe signal and an inverted clock signal.  
     
     
         13 . The random access memory of  claim 12 , wherein the control circuit comprises a latch configured to receive a delay chain output signal from the delay chain and an output signal from the logic circuit.  
     
     
         14 . The random access memory of  claim 13 , wherein the control circuit comprises a NOR gate configured to receive the strobe signal and a latch output signal from the latch.  
     
     
         15 . A random access memory comprising: 
 a signal generation circuit comprising: 
 an enable controller configured to provide an enable signal; and  
 a controlled buffer configured to receive the enable signal and a strobe signal,  
   wherein the enable controller and the controlled buffer are configured to generate a    pulse at one edge of the strobe signal for each cycle of a clock signal; and    a plurality of latching circuits, wherein each latching circuit is configured to receive the strobe signal to latch data into the latching circuit and the pulse to block noise on the strobe signal from latching data into the latching circuit.    
     
     
         16 . The random access memory of  claim 15 , wherein each latching circuit in the plurality of latching circuits comprises a first latching stage, a second latching stage and a third latching stage.  
     
     
         17 . The random access memory of  claim 16 , wherein the pulse latches data into the third latching stage.  
     
     
         18 . The random access memory of  claim 16 , wherein the first latching stage and the second latching stage are configured to receive the strobe signal to latch data into the first latching stage and the second latching stage.  
     
     
         19 . A random access memory comprising: 
 a plurality of signal generation circuits, wherein each signal generation circuit comprises: 
 an enable controller configured to provide an enable signal; and  
 a controlled buffer configured to receive the enable signal and a strobe signal,  
   wherein the enable controller and the controlled buffer are configured to generate a    pulse at one edge of the strobe signal for each cycle of a clock signal; and    a plurality of latching circuits, wherein each latching circuit is configured to receive the pulse from one signal generation circuit in the plurality of signal generation circuits to block noise on the strobe signal from latching data into the latching circuit.    
     
     
         20 . The random access memory of  claim 19 , wherein each latching circuit in the plurality of latching circuits comprises a first latching stage, a second latching stage and a third latching stage.  
     
     
         21 . The random access memory of  claim 20 , wherein the pulse latches data into the third latching stage.  
     
     
         22 . The random access memory of  claim 20 , wherein the first latching stage and the second latching stage are configured to receive the strobe signal to latch data into the first latching stage and the second latching stage.  
     
     
         23 - 31 . (canceled)  
     
     
         32 . A random access memory comprising: 
 a first circuit configured to receive a strobe signal and a clock signal and to provide pulses in response to transitions in the strobe signal, wherein the first circuit is configured such that only one pulse is provided in response to a transition in the strobe signal after each edge of a predetermined type of the clock signal; and    a second circuit configured to receive the strobe signal to latch data into the second circuit in response to the strobe signal, and to receive the pulses to re-latch the latched data into the second circuit after the transitions in the strobe signal.    
     
     
         33 . The random access memory of  claim 32 , wherein the second circuit comprises a first latching stage, a second latching stage and a third latching stage.  
     
     
         34 . The random access memory of  claim 33 , wherein the second circuit is configured to receive the strobe signal to latch data into the first latching stage and the second latching stage.  
     
     
         35 . Then random access memory of  claim 33 , wherein the second circuit is configured to receive the pulses to re-latch the latched data into the third latching stage.  
     
     
         36 . A method for rejecting post-amble noise on a data strobe signal in a random access memory, the method comprising: 
 receiving the strobe signal and a clock signal;    generating pulses in response to transitions in the strobe signal such that only one pulse is provided in response to a transition in the strobe signal after each edge of a predetermined type of the clock signal;    receiving the strobe signal to latch data into a second circuit; and    receiving the pulses to re-latch the latched data into the second circuit after the transitions in the strobe signal.    
     
     
         37 . The method of  claim 36 , wherein receiving the strobe signal to latch data into the second circuit comprises receiving the strobe signal to latch data into a first latch stage and a second latch stage of the second circuit.  
     
     
         38 . The method of  claim 37 , wherein receiving the pulses to re-latch the latched data into the second circuit comprises receiving the pulses to re-latch the latched data into a third latch stage of the second circuit.