Computer-implemented methods, processors, and systems for creating a wafer fabrication process

Abstract

Computer-implemented methods, processors, and systems for creating a wafer fabrication process are provided. One computer-implemented method includes determining individual error budgets for different parameters of the wafer fabrication process based on an overall error budget for the wafer fabrication process and simulated images that illustrate how reticle design data will be printed on a wafer at different values of the different parameters. The method also includes creating the wafer fabrication process based on the overall error budget and the individual error budgets.

1 . A computer-implemented method for creating a wafer fabrication process, comprising: 
 determining individual error budgets for different parameters of the wafer fabrication process based on an overall error budget for the wafer fabrication process and simulated images that illustrate how reticle design data will be printed on a wafer at different values of the different parameters; and    creating the wafer fabrication process based on the overall error budget and the individual error budgets.    
     
     
         2 . The method of  claim 1 , wherein the wafer fabrication process comprises a lithography process.  
     
     
         3 . The method of  claim 1 , wherein the wafer fabrication process comprises an etch process.  
     
     
         4 . The method of  claim 1 , wherein the wafer fabrication process comprises a device design process, a reticle manufacturing process, and a lithography process.  
     
     
         5 . The method of  claim 1 , wherein the wafer fabrication process comprises a device design process, a reticle manufacturing process, a lithography process, and an etch process.  
     
     
         6 . The method of  claim 1 , wherein said creating comprises selecting operating set points and levels of control for the different parameters based on the overall error budget and the individual error budgets.  
     
     
         7 . The method of  claim 1 , wherein said creating comprises modifying predetermined operating set points for the different parameters based on the overall error budget and the individual error budgets.  
     
     
         8 . The method of  claim 1 , wherein said creating comprises selecting operating set points and levels of control for the different parameters based on the overall error budget and how variations in the individual error budgets affect how the reticle design data will be printed on the wafer.  
     
     
         9 . The method of  claim 1 , wherein the individual error budget for one of the different parameters is determined as a function of the individual error budget for another of the different parameters.  
     
     
         10 . The method of  claim 1 , wherein said creating comprises selecting operating set points and levels of control for at least two of the different parameters based on the overall error budget and a function describing an interrelated effect of the individual error budgets for the at least two of the different parameters on how the reticle design data will be printed on the wafer.  
     
     
         11 . The method of  claim 1 , wherein said creating comprises selecting operating set points and levels of control for the different parameters based on the overall error budget, the individual error budgets, and controllability of the different parameters.  
     
     
         12 . The method of  claim 1 , wherein said creating comprises selecting operating set points and levels of control for the different parameters based on the overall error budget, the individual error budgets, and cost of implementing the levels of control.  
     
     
         13 . The method of  claim 1 , wherein the different parameters comprise all parameters of the wafer fabrication process that can alter how the reticle design data will be printed on the wafer.  
     
     
         14 . The method of  claim 1 , further comprising generating the simulated images by generating a first simulated image illustrating how the reticle design data will be printed on a reticle using a reticle manufacturing process and generating the simulated images using the first simulated image.  
     
     
         15 . The method of  claim 1 , wherein the different values span a predetermined process window for the different parameters.  
     
     
         16 . The method of  claim 1 , further comprising detecting defects in the simulated images, wherein said determining comprises determining the individual error budgets based on the overall error budget and the defects in the simulated images.  
     
     
         17 . The method of  claim 1 , wherein the different parameters comprise different characteristics of the reticle design data.  
     
     
         18 . The method of  claim 17 , further comprising creating a design process for the reticle design data based on the overall error budget and the individual error budgets for the different parameters.  
     
     
         19 . The method of  claim 17 , further comprising altering the reticle design data based on the overall error budget and the individual error budgets for the different parameters.  
     
     
         20 . A processor configured to perform a method for creating a wafer fabrication process, wherein the method comprises: 
 determining individual error budgets for different parameters of the wafer fabrication process based on an overall error budget for the wafer fabrication process and simulated images that illustrate how reticle design data will be printed on a wafer at different values of the different parameters; and    creating the wafer fabrication process based on the overall error budget and the individual error budgets.    
     
     
         21 . A system configured to create a wafer fabrication process, comprising: 
 a simulation engine configured to generate simulated images illustrating how reticle design data will be printed on a wafer at different values of different parameters of the wafer fabrication process; and    a processor configured to determine individual error budgets for the different parameters based on an overall error budget for the wafer fabrication process and the simulated images and to create the wafer fabrication process based on the overall error budget and the individual error budgets.