Methods for selective integration of airgaps and devices made by such methods

Abstract

Damascene stacks for use in semiconductor devices and methods for making such stacks are disclosed. An example damascene stack includes a substantially planar lower liner layer and a patterned sacrificial dielectric layer disposed on top of the lower liner layer, where the patterned sacrificial dielectric layer includes an interconnect structure of the damascene stack. The example damascene stack further includes a substantially planar upper liner layer disposed on top of the patterned sacrificial dielectric layer, where the upper liner layer being formed of a material that is resistant to etching by a first etch compound. There is at least one plug-hole in the upper liner layer, where the at least one plug-hole is (i) adjacent to the interconnect structure and (ii) formed by locally converting a portion of the upper liner layer to be etchable by the first etch compound and removing the locally converted portion of the upper liner layer using the first etch compound. The example damascene stack still further includes at least one air gap formed by removing at least a portion of the sacrificial dielectric layer through the at least one plug-hole in said upper liner layer.

1 - 23 . (canceled)  
   
   
       24 . A damascene stack for use in a semiconductor device, the damascene stack comprising: 
 a substantially planar lower liner layer;    a patterned sacrificial dielectric layer disposed on top of the lower liner layer, the patterned sacrificial dielectric layer including an interconnect structure of the damascene stack;    a substantially planar upper liner layer disposed on top of the patterned sacrificial dielectric layer, the upper liner layer being formed of a material that is resistant to etching by a first etch compound;    at least one plug-hole in the upper liner layer, wherein the at least one plug-hole is (i) adjacent to the interconnect structure and (ii) formed by locally converting a portion of the upper liner layer to be etchable by the first etch compound and removing the locally converted portion of the upper liner layer using the first etch compound; and    at least one air gap formed by removing at least a portion of the sacrificial dielectric layer through the at least one plug-hole in the upper liner layer.    
   
   
       25 . The damascene stack of  claim 24 , wherein the material of the upper liner layer and the material of the lower liner layer are substantially the same material and the damascene stack further comprises at least one plug-hole in the lower liner layer being (i) adjacent to the interconnect structure and (ii) formed by locally converting a portion of the lower liner layer to be etchable by the first etch compound and removing the locally converted portion of the lower liner layer using the first etch compound.  
   
   
       26 . The damascene stack of  claim 25 , further comprising a basis layer disposed underneath the lower liner layer, the basis layer being formed of a material that is resistant to etching by a second etch compound.  
   
   
       27 . The damascene stack of  claim 25 , further comprising a basis layer disposed underneath the lower liner layer, the basis layer being formed of a material that is resistant to etching by a second etch compound and resistant to etching by the first etch compound.  
   
   
       28 . The damascene stack of  claim 25 , wherein the basis layer is used as an etchstop layer for patterning the interconnect structure in the dielectric layer.  
   
   
       29 . The damascene stack of  claim 25 , wherein local conversion of the upper and lower liner layer occurs during patterning of the interconnect structure using a dry etch sequence.  
   
   
       30 . The damascene stack of  claim 24 , wherein the damascene stack comprises a single damascene structure.  
   
   
       31 . The damascene stack of  claim 24 , wherein the damascene stack comprises a dual damascene structure.  
   
   
       32 . The damascene stack of  claim 24 , wherein the interconnect structure is formed from a conductive material.  
   
   
       33 . The damascene stack of  claim 32 , wherein the interconnect structure comprises a diffusion barrier layer.  
   
   
       34 . The damascene stack of  claim 24 , wherein the upper liner layer is formed of a carbon containing Si compound.  
   
   
       35 . The damascene stack of  claim 24 , wherein both the upper and lower liner layer are formed of a carbon containing Si compound.  
   
   
       36 . The damascene stack of  claim 24 , wherein the at least one sacrificial dielectric layer is formed of a Si containing dielectric material.  
   
   
       37 . The damascene stack of  claim 24 , wherein the upper liner layer is used as a hardmask layer for patterning the interconnect structure in the dielectric layer.  
   
   
       38 . The damascene stack of  claim 24 , wherein the lower liner layer is used as an etchstop layer for patterning the interconnect structure in the dielectric layer.  
   
   
       39 . The damascene stack of  claim 24 , wherein local conversion of the upper liner layer occurs prior to formation of the interconnect structure.  
   
   
       40 . The damascene stack of  claim 24 , wherein local conversion of the upper liner layer occurs during patterning of the interconnect structure using a dry etch sequence.  
   
   
       41 . The damascene stack of  claim 24 , wherein the upper liner layer is formed from a carbon containing Si compound that is locally converted into an oxygen containing Si compound for forming the at least one plug-hole in the upper liner layer.  
   
   
       42 . The damascene stack of  claim 41 , wherein locally converting the upper liner layer from the carbon containing Si compound to the oxygen containing Si compound is accomplished using an oxidizing plasma.  
   
   
       43 . The damascene stack of  claim 24 , wherein removing the portion of the sacrificial dielectric layer through the at least one plug-hole in the upper liner layer is accomplished using an etching compound comprising HF.