Memory device

Abstract

Disclosed are a phase change memory with improved retention characteristic of a phase change device, and a method for refreshing the phase change memory. The fact that a memory is a DRAM interface compatible memory is exploited. There are provided dummy cells stressed in accordance with the number of times of read and write operations. Changes in the resistance value of the dummy cells are detected by comparator circuits. If the resistance value have been changed beyond a predetermined reference value (that is, changed to a low resistance), a refresh request circuit requests an internal circuit, not shown, to effect refreshing. The memory cells and the dummy cells are transitorily refreshed and correction is made for variations in the programmed resistance value of the phase change devices to assure the margin as well as to improve retention characteristic.

1 . A memory device comprising: 
 a plurality of bit lines and a plurality of word lines;    a plurality of memory cells, each of said memory cells provided at an intersection of an associated bit line and an associated word line, each of said memory cells including a programmable resistance element; and    a control circuit for performing control to carry out a refresh operation of said memory cell responsive to a change in a resistance value of said memory cell.    
     
     
         2 . The memory device according to  claim 1 , wherein said memory cell comprises: 
 a memory cell transistor and said programmable resistor element which are connected in series between said bit line and a first power supply;    said memory cell transistor having a control terminal connected to said word line.    
     
     
         3 . The memory device according to  claim 1 , wherein said programmable resistor element comprises a phase change material.  
     
     
         4 . The memory device according to  claim 1 , further comprising: 
 a dummy cell including a programmable resistor element;    a comparator circuit for monitoring the state of said dummy cell to detect a change in the state of the dummy cell; and    a refresh request circuit for generating and outputting a refresh request based on detection of the change in the state of the dummy cell in said comparator circuit.    
     
     
         5 . The memory device according to  claim 4 , wherein said dummy cell comprises: 
 a set dummy cell and a reset dummy cell, into which the state corresponding to the states of ‘1’ and ‘0’ of data have been written, respectively.    
     
     
         6 . The memory device according to  claim 4 , wherein said comparator circuit compares a reference resistance or a constant current with that of said dummy cell.  
     
     
         7 . The memory device according to  claim 4 , wherein said dummy cell is disposed in a memory cell area and selected by the same word line as that for the memory cell to effect dummy cell read.  
     
     
         8 . The memory device according to  claim 7 , wherein said dummy cell comprises: 
 a memory cell transistor and said programmable resistor element which are connected in series between a first power supply and a bit line to which said dummy cell is connected;    said memory cell transistor having a control terminal connected to a word line in common to said memory cell.    
     
     
         9 . The memory device according to  claim 8 , further comprising 
 a bias circuit for managing control to apply a stress to the bit line to which said dummy cell is connected, said stress being applied when the memory cell is selected.    
     
     
         10 . The memory device according to  claim 1 , further comprising: 
 a sense amplifier for sensing and amplifying data written in said memory cell; and    a verification amplifier for comparing and detecting the data write state in said memory cell at the time of refreshing;    said verification amplifier effecting write verification at the time of refreshing.    
     
     
         11 . The memory device according to  claim 10 , wherein said sense amplifier differs from said verification amplifier as to a reference current for decision, said sense amplifier being set so as to have operation margin.  
     
     
         12 . The memory device according to  claim 1 , further comprising 
 a data register for holding data read and transferred from a memory cell at the time of refreshing.    
     
     
         13 . The memory device according to  claim 12 , wherein the value of said data register is referenced at the time of the refreshing to set only the cell of the first one of two states temporarily to a second state.  
     
     
         14 . The memory device according to  claim 12 , further comprising 
 a write pulse control circuit for programming the cells all set to the second state at the time of the refreshing to the first state transitorily stepwise.    
     
     
         15 . The memory device according to  claim 12 , wherein, when all of the cells are in said first state, the values of said data register are referenced and only cells of data in said second state are set to the second state.  
     
     
         16 . The memory device according to  claim 12 , wherein the values of said data register are referenced and only cells in the first state are set to said first state.  
     
     
         17 . The memory device according to  claim 12  wherein the values of said data register are referenced at the time of refreshing and only cells in the first state are overwritten to said first state.  
     
     
         18 . The memory device according to  claim 12 , wherein the values of said data register are referenced at the time of refreshing and cells in the first state are all set said first state.  
     
     
         19 . The memory device according to  claim 12 , wherein the values of said data register are referenced and only cells which are to be in the second state are set to said second state.  
     
     
         20 . The memory device according to  claim 1 , further comprising: 
 a counter for counting the number of times of read; and    means for monitoring the number of times of read and issuing a refresh request to an internal circuit when the number of times of read has reached a predetermined value.    
     
     
         21 . The memory device according to  claim 1 , further comprising 
 means for comparing a reference current by a reference resistance or a constant current with read data from a memory cell and detecting that a predetermined offset has been produced to issue a refresh request to an internal circuit.    
     
     
         22 . A memory device having a plurality of memory cells, each including a phase change device, said memory device comprising: 
 a dummy cell including a phase change device, said dummy cell being subjected to a stress in accordance with the number of times of read and write operations;    a circuit for detecting a change in a resistance value of the phase change device of said dummy cell; and    refresh requesting means for issuing a refresh request when the resistance value of said phase change device in said dummy cell has been changed beyond a predetermined reference value;    said memory cell and the dummy cell being refreshed based on said refresh request.    
     
     
         23 . A memory device having a plurality of memory cells, each including a phase change device, said memory device comprising: 
 a counter for counting the number of times of read; and    means for monitoring the number of times of read and for issuing a refresh request when the number of times of read has reached a preset value.    
     
     
         24 . The memory device according to  claim 22 , further comprising: 
 a data register for holding data read from said memory cell at the time of refreshing; and    a verification amplifier for comparing and detecting the write state of data in said memory cell at the time of refreshing; wherein    data in said memory cell is read at the time of refreshing and temporarily transferred to said data register;    the value of said data register is then referenced and only the cells in the first state are written to a second state;    the first state data is set in said verification amplifier;    the writing of the first state to the cell is carried out while verification read being carried out;    the current comparison with a predetermined resistance is executed and the writing is discontinued in the cell where the predetermined resistance has been reached and writing is continued for other cells; and wherein    the value of said data register is referenced in re-writing and writing of the second state is made only for cells of the second cell.    
     
     
         25 . A memory device having a plurality of memory cells, each including a phase change device, said memory device comprising: 
 first and second reference current circuits for supplying first and second reference currents, corresponding to first and second states, respectively; and    refresh requesting means for comparing the currents flowing through said memory cells to said first and second reference currents and for issuing a refresh request when a predetermined offset has been produced;    said memory cells being refreshed based on said refresh request.    
     
     
         26 . The memory device according to  claim 25 , wherein the cells in the first and second states are read; 
 if the cells read are the cells of the second state, the cells are overwritten to said second state; the overwritten cells in said second state being written to the first state and again written again to the second state of the normal current and the voltage; and wherein    if the cells read are the cells of the first state, the cells are set to the second state and again restored to said first state.