Structure and method of forming a notched gate field effect transistor

Abstract

A structure and method of forming a notched gate MOSFET. A gate dielectric is formed on the surface of an active area on the semiconductor substrate. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium. The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer. One or more other processing steps are preferably performed in completing the transistor.

1 . A method of producing a metal oxide semiconductor field effect transistor having a notched gate structure, comprising: 
 defining an active area of a substrate;    forming a gate dielectric on said active area;    forming a first gate conductor layer of polysilicon on said gate dielectric;    forming a second gate conductor layer of silicon germanium over the polysilicon layer, the silicon germanium layer being broader than, and overhanging the polysilicon layer; and    completing the transistor structure.    
   
   
       2 . The method of  claim 1 , wherein the step of forming the first gate conductor layer includes laterally etching the polysilicon of the first gate conductor layer selective to the silicon germanium of the second gate conductor layer.  
   
   
       3 . The method of claim I, further comprising forming a layer of silicide over the silicon germanium layer.  
   
   
       4 . The method of  claim 3 , wherein the substrate is subjected to a source/drain extension implant before the layer of silicide is formed.  
   
   
       5 . The method of  claim 3 , further comprising forming insulating spacers on sidewalls of the polysilicon layer and the silicon germanuim layer.  
   
   
       6 . The method of  claim 5 , wherein the insulating spacers are formed by depositing a material including at least one of silicon dioxide and silicon nitride on exposed surfaces of the first and the second gate conductor layers, and anisotropically, vertically etching the deposited material.  
   
   
       7 . The method of  claim 6 , wherein the layer of silicide is formed in self-aligned manner by forming a layer of polysilicon over the silicon germanium layer, depositing a metal after forming the insulating spacers, and reacting the metal with the polysilicon layer to form the self-aligned silicide.  
   
   
       8 . The method of  claim 1 , wherein a third gate conductor layer of polysilicon is formed over the silicon germanium layer, a masking layer is formed over the third gate conductor layer, the masking layer and the first, second and third gate conductor layers are then patterned by vertical etching, stopping on the gate dielectric, and thereafter, the first gate conductor layer is etched laterally such that the silicon germanium layer is broader than and overhangs thed first gate conductor layer.  
   
   
       9 . The method of  claim 8 , wherein the first gate conductor layer is laterally etched by isotropic wet etching, selective to the silicon germanium layer.  
   
   
       10 . The method of  claim 9 , wherein the isotropic wet etching is performed by alternating steps of rinsing the silicon germanium layer to form a protective oxide thereon and etchiing the first gate conductor layer.  
   
   
       11 . The method of  claim 1 , further comprising the step of implanting Lightly Doped Drain regions into the surface of the substrate.  
   
   
       12 . The method of claim I  1 , wherein implanted ions during the Lightly Doped Drain implanting step are driven into surface of the substrate by heating the substrate.  
   
   
       13 . A metal oxide semiconductor field effect transistor having a notched gate conductor structure, comprising: 
 a gate dielectric formed on the surface of a semiconductor substrate;    a gate conductor stack overlying the gate dielectric, the gate conductor stack including    a polysilicon layer formed over the gate dielectric;    a silicon germanium layer formed over the polysilicon layer, the silicon germanium layer being broader than, and overhanging the polysilicon layer; and    source and drain regions formed in the substrate on opposing sides of the gate conductor stack.    
   
   
       14 . The metal oxide semiconductor field effect transistor of  claim 13 , further including a silicide layer overlying the silicon germanium layer.  
   
   
       15 . The metal oxide semiconductor field effect transistor of  claim 13 , further comprising source and drain extensions overlapping the source and drain regions, implanted into the substrate.  
   
   
       16 . The metal oxide semiconductor field effect transistor of  claim 15 , further comprising insulating spacers on sidewalls of the polysilicon layer and the silicon germanium layer.  
   
   
       17 . The metal oxide semiconductor field effect transistor of  claim 16 , wherein the insulating spacers comprise at least one of silicon dioxide and silicon nitride.  
   
   
       18 . The metal oxide semiconductor field effect transistor of  claim 14 , wherein the layer of silicide is a self-aligned layer.  
   
   
       19 . The metal oxide semiconductor field effect transistor of  claim 13 , further comprising implanting pocket lightly doped drain regions under sidewalls of the gate conductor stack.  
   
   
       20 . The metal oxide semiconductor field effect transistor of  claim 13 , further comprising a silicide formed in contact with top surfaces of the source and drain regions.