Method of providing a CMOS output stage utilizing a buried power buss

Abstract

A method of providing a CMOS output stage is disclosed. The method includes providing a substrate, providing at least two wells above the substrate, providing a plurality of slots through the at least two wells into the substrate, oxidizing each of the plurality of slots, and filling each of the plurality of slots with a metal to provide a plurality of power busses. This allows power busses to be established wherever necessary without causing any circuit issues since the power buss metal is isolated by the oxide. One of the power busses provides a ground. One of the power busses provides an output. One of the power busses provides a power connector.

1 . A method of providing a complimentary metal-oxide semiconductor (CMOS) output stage, the method comprising: 
 providing a substrate;    providing at least two wells above the substrate;    providing a plurality of slots through the at least two wells into the substrate;    oxidizing each of the plurality of slots; and    filling each of the plurality of slots with a metal to provide a plurality of power busses, wherein one of the plurality of power busses provides a ground, one of the plurality of power busses provides an output, and one of the plurality of power busses provides a power connector.    
   
   
       2 . The method of  claim 1 , wherein each of the plurality of slots is filled with the metal via a chemical vapor deposition (CVD) metal deposition process.  
   
   
       3 . The method of  claim 1 , wherein each of the plurality of slots is filled with the metal by applying the metal in sputtered layers and planarizing the metal to remove the metal in the fields without the use of a masking.  
   
   
       4 . The method of  claim 1 , wherein the ground power buss is not oxidized at the interface between the metal and the substrate.  
   
   
       5 . The method of  claim 4 , wherein the oxide is removed from a bottom of one of the plurality of slots prior to metallization.  
   
   
       6 . The method of  claim 1 , wherein ends of the at least two wells are shortened to minimize the size of the CMOS output stage.  
   
   
       7 . The method of  claim 6 , wherein the at least two wells are in close proximity to each other, which further minimizes the size of the CMOS output stage.  
   
   
       8 . The method of  claim 6 , wherein minimizing the size of the CMOS output stage results in lowered on resistance (R on ) lowered capacitance, reduced die size, higher speed, and improved protection again electromigration.  
   
   
       9 . The method of  claim 1 , wherein a current path from the at least two wells to the substrate is eliminated as a result of the plurality of slots being oxidized, which increases the snap back voltage and sustaining current.  
   
   
       10 . The method of  claim 1 , wherein heat transfer capability of the metal in each of the plurality of slots through silicon is ten times better than through oxide.  
   
   
       11 . The method of  claim 1 , wherein heat transfer capability of the metal in each of the plurality of slots through oxide is twenty times better than through air.  
   
   
       12 . The method of  claim 1 , further comprising: 
 connecting a drain of an N-channel and a drain of a P-channel via one of the plurality of oxidized and metalized slots.    
   
   
       13 . The method of  claim 12 , wherein the one oxidized and metalized slot also allows the CMOS output stage to provide a short between the two drains.