Wrapper testing circuits and method thereof for system-on-a-chip

Abstract

A wrapper testing circuit and method thereof for System-On-a-Chip is provided for electrical tests of core circuits of an integrated circuit. The testing circuit includes a decoding logic with an encoding table for receiving test signals and delivering control signals in response to the test signals according to the table; a plurality of registers for saving the control signals temporarily and delivering the control signals to the core circuits; a bypass circuit for delivering the test signals; and an instruction register for saving the test signals temporarily and refreshing the data in the registers and the bypass circuits after the decoding logic issues the control signals. The encoding of the control signals is completed in one period. Compared with the serial encoding in the prior art, test time is reduced.

1 . A wrapper testing circuit of system-on-a-chip for electrical tests of a core circuit of an integrated circuit, the core having input ports and output ports, the circuit comprising: 
 a decoding logic having a signal encoding table, for receiving a test signal and thereby    issuing a control signal according to the signal encoding table;    a plurality of Wrapper Boundary registers for temporarily storing the control signal and delivering the control to the core circuit;    a bypass circuit for transferring the test signal from the decoding logic; and    an instruction register for temporarily storing the test signal from the bypass circuit, and changing data in the Wrapper Boundary registers and the bypass circuit after the control signal is issued by the decoding logic, thereby testing the core circuit.    
   
   
       2 . The wrapper testing circuit of  claim 1 , wherein the decoding logic issues the control signal in one clock after receiving the test signal.  
   
   
       3 . The wrapper testing circuit of  claim 1  further comprises a plurality of multiplexers connected to the plurality of Wrapper Boundary registers.  
   
   
       4 . The wrapper testing circuit of  claim 1 , wherein the instruction register is a one-bit register.  
   
   
       5 . A wrapper testing circuit of system-on-a-chip for electrical tests of a core circuit of a integrated circuit, the core having input ports and output ports, the circuit comprising: 
 a decoding logic having a signal encoding table, for receiving a test signal and thereby issuing a control signal according to the signal encoding table;    a plurality of Wrapper Boundary registers for temporarily storing the control signal and delivering the control to the core circuit;    a plurality of first multiplexers for receiving the test signal and the control signal, and outputting the control signal to the Wrapper Boundary register;    a bypass circuit for transferring the test signal from the decoding logic; and    an instruction register for temporarily storing the test signal from the bypass circuit, and changing data in the Wrapper Boundary registers and the bypass circuit after the control signal is issued by the decoding logic, thereby testing the core circuit.    
   
   
       6 . The wrapper testing circuit of  claim 5 , wherein the decoding logic issues the control signal in one clock after receiving the test signal.  
   
   
       7 . The wrapper testing circuit of  claim 5  further comprises a second multiplexer and a third multiplexer connected to the plurality of Wrapper Boundary registers respectively.  
   
   
       8 . The wrapper testing circuit of  claim 5 , wherein the instruction register is a one-bit register.  
   
   
       9 . A wrapper testing method of system-on-a-chip for electrical tests of a core circuit of a integrated circuit, the core having input ports and output ports, the method comprising steps of: 
 providing an encoding table;    inputting a test signal and thereby issuing a control signal according to the encoding table;    storing the control signal temporarily and delivering the control signal to the core circuit; and    storing the test signal temporarily and changing the test signal and the control signal stored temporarily for testing the core circuit after the control signal is issued.    
   
   
       10 . The wrapper testing method of  claim 9 , wherein the control signal is outputted within one clock after the control signal is received.