Incremental redundancy memory

Abstract

IR memory for an EGPRS receiver of a mobile station which receives data from a base station, by means of a data transmission channel, whereby the IR memory comprises a first memory region, for the buffering of a Particular number of data blocks with a given first data resolution and a second memory region for the buffering of erroneously-decoded data blocks. The second memory region stores the erroneously-decoded data blocks with a second data resolution which is lower than the first data resolution.

1 . An IR memory for an EGPRS receiver of a mobile station, which receives data from a base station via a data transmission channel, the IR memory having: 
 a) a first memory area for buffer-storing a specific number of data blocks with a predetermined first data resolution;    b) a second memory area for buffer-storing erroneously decoded data blocks,    c) the second memory area storing the erroneously decoded data blocks with a second data resolution, which is lower than the first data resolution, and    d) it being possible for the second data resolution with which the erroneously decoded data blocks are stored in the second memory area of the IR memory to be changed over adaptively between different resolution levels in a manner dependent on a burst data transmission signal quality measured by the receiver.    
   
   
       2 . The IR memory as claimed in  claim 1 , wherein the number of data blocks that can be stored in the first memory area of the IR memory depends on the internal signal delay within the mobile station.  
   
   
       3 . The IR memory as claimed in  claim 1 , wherein the number of data blocks that can be stored in the second memory area of the IR memory depends on the polling period of the data transmission channel and on the round trip delay.  
   
   
       4 . The IR memory as claimed in  claim 1 , wherein the resolution levels of the second data resolution are 2 bits, 3 bits or 4 bits.  
   
   
       5 . The IR memory as claimed in  claim 1 , wherein the first data resolution is 5 bits.  
   
   
       6 . The IR memory as claimed in  claim 1 , wherein the IR memory is connected, on the input side, to a reception buffer memory for data blocks.  
   
   
       7 . The IR memory as claimed in  claim 1 , wherein the IR memory is connected to a decoder on the output side.  
   
   
       8 . The IR memory as claimed  claim 1 , wherein the data blocks are RLC data blocks.  
   
   
       9 . The IR memory as claimed in  claim 1 , wherein the data blocks are MCS-coded.