Dual stage DRAM memory equalization

Abstract

A memory device equilibrates voltages in a bit line pair to a reduced voltage level. The reduced equilibrate voltage level can be achieved by separating the conventional equilibrate process so that the positive portion and the negative portion of the sense amplifier are equilibrated at different times. Bit line equilibration can be associated with either the equilibrate step associated with the positive portion of the sense amplifier or the equilibrate step associated with the negative portion of the sense amplifier.

1 - 26 . (canceled)  
   
   
       27 . A method for equilibrating a first bit line with a second bit line in a memory device, comprising: 
 setting said first bit line to a first potential;    setting said second bit line to a second potential;    at a first time, 
 applying a first control signal to a first common node of a sense amplifier to equilibrate a first portion of said sense amplifier, said sense amplifier being coupled to said first and second bit lines,  
 coupling said first bit line to said second bit line, and  
 coupling said first and second bit lines to a third potential different from said first potential and said second potential;  
   at a second time, different from said first time, 
 applying a second control signal to a second common node of said sense amplifier to equilibrate a second portion of said sense amplifier.  
   
   
   
       28 . The method of  claim 27 , wherein one of said first potential and said second potential is a DC supply voltage, another of said first potential and said second potential is a ground potential.  
   
   
       29 . The method of  claim 27 , further comprising: 
 delaying a copy of said first control signal to produce said second control signal.    
   
   
       30 . The method of  claim 27 , wherein said first portion of said sense amplifier comprises a negative portion of said sense amplifier.  
   
   
       31 . The method of  claim 27 , wherein said second portion of said sense amplifier comprises a positive portion of said sense amplifier.  
   
   
       32 . The method of  claim 27 , wherein said third potential comprises a potential between said first potential and said second potential.  
   
   
       33 . A memory device, comprising: 
 a control circuit;    a plurality of bit lines, organized into a plurality of pairs of associated bit lines;    a plurality of word lines;    a plurality of memory cells, each memory cell being coupled to one of said plurality of bit lines and one of said plurality of word lines; and    a plurality of sense amplifiers, each sense amplifier being coupled to said control circuit and to a respective pair of associated bit lines, each sense amplifier having a first portion with a first common node and a second portion with a second common node,    wherein said control circuit performs an equilibrate operation on one pair of associated bit lines by 
 at a first time, applying a first control signal to the first common node to equilibrate the first portion of the sense amplifier coupled to said one pair of associated bit lines, and 
 coupling said associated pair of bit lines with each other and with a source of a third potential different from said first potential and said second potential; and  
 
 at a second time different from said first time, 
 applying a second control signal to the second common node to equilibrate the second portion of the second portion of the sense amplifier coupled to said one pair of associated bit lines.  
 
   
   
   
       34 . The memory device of  claim 33 , wherein one of said first potential and said second potential is a DC supply voltage, another of said first potential and said second potential is a ground potential.  
   
   
       35 . The memory device of  claim 33 , wherein said control circuit comprises a delay device that delays a copy of said first control signal to produce said second control signal.  
   
   
       36 . The method of  claim 33 , wherein said first portion of said sense amplifier comprises a negative portion of said sense amplifier.  
   
   
       37 . The method of  claim 33 , wherein said second portion of said sense amplifier comprises a positive portion of said sense amplifier.  
   
   
       38 . The method of  claim 33 , wherein said third potential comprises a potential between said first potential and said second potential.  
   
   
       39 . A system, comprising: 
 a bus;    a processor, coupled to said bus; and    a memory, coupled to said bus, said memory further comprising: 
 a control circuit;  
 a plurality of bit lines, organized into a plurality of pairs of associated bit lines;  
 a plurality of word lines;  
 a plurality of memory cells, each memory cell being coupled to one of said plurality of bit lines and one of said plurality of word lines; and  
 a plurality of sense amplifiers, each sense amplifier being coupled to said control circuit and to a respective pair of associated bit lines, each sense amplifier having a first portion with a first common node and a second portion with a second common node,  
 wherein said control circuit performs an equilibrate operation on one pair of associated bit lines by 
 at a first time, 
 applying a first control signal to the first common node to equilibrate the first portion of the sense amplifier coupled to said one pair of associated bit lines, and  
 coupling said associated pair of bit lines with each other and with a source of a third potential different from said first potential and said second potential; and  
 
 at a second time different from said first time, 
 applying a second control signal to the second common node to equilibrate the second portion of the second portion of the sense amplifier coupled to said one pair of associated bit lines.  
 
 
   
   
   
       40 . A method for equilibrating a first bit line and a second bit line coupled to a sense amplifier, comprising: 
 setting said first bit line to a first potential;    setting said second bit line to a second potential;    coupling an equilibrate control signal to a first common node of said sense amplifier to equilibrate a first portion of said sense amplifier while coupling said first and second bit lines to a third potential different from said first and second potential; and    coupling a delayed equilibrate control signal, generated by delaying the equilibrate control signal, to a second common node of said sense amplifier to equilibrate a second portion of said sense amplifier.    
   
   
       41 . The method of  claim 40 , wherein one of said first potential and said second potential is a DC supply voltage, and another of said first potential and said second potential is a ground potential.  
   
   
       42 . The method of  claim 40 , wherein said first portion of said sense amplifier comprises a negative portion of said sense amplifier.  
   
   
       43 . The method of  claim 40 , wherein said second portion of said sense amplifier comprises a positive portion of said sense amplifier.  
   
   
       44 . The method of  claim 40 , wherein said third potential comprises a potential between said first potential and said second potential.  
   
   
       45 . A method for equilibrating a first bit line and a second bit line coupled to a sense amplifier, comprising: 
 setting said first bit line to a first potential;    setting said second bit line to a second potential;    coupling an equilibrate control signal to a first common node of said sense amplifier to equilibrate a second portion of said sense amplifier; and    coupling a delayed equilibrate control signal, generated by delaying the equilibrate control signal, to a second common node of said sense amplifier to equilibrate a first portion of said sense amplifier while coupling said first and second bit lines to a third potential different from said first and second potential.    
   
   
       46 . The method of  claim 45 , wherein one of said first potential and said second potential is a DC supply voltage, and another of said first potential and said second potential is a ground potential.  
   
   
       47 . The method of  claim 45 , wherein said first portion of said sense amplifier comprises a negative portion of said sense amplifier.  
   
   
       48 . The method of  claim 45 , wherein said second portion of said sense amplifier comprises a positive portion of said sense amplifier.  
   
   
       49 . The method of  claim 45 , wherein said third potential comprises a potential between said first potential and said second potential.  
   
   
       50 . A memory device, comprising: 
 a control circuit for generating a first control signal;    a delay device for generating a second control signal by delaying said first control signal;    a plurality of bit lines, organized into a plurality of pairs of associated bit lines;    a plurality of word lines;    a plurality of memory cells, each memory cell being coupled to one of said plurality of bit lines and one of said plurality of word lines; and    a plurality of sense amplifiers, each sense amplifier being coupled to said control circuit and to a respective pair of associated bit lines, each sense amplifier having a first portion with a first common node and a second portion with a second common node,    wherein said control circuit performs an equilibrate operation on one pair of associated bit lines by 
 applying the first control signal to the first common node to equilibrate the first portion of the sense amplifier coupled to said one pair of associated bit lines, while coupling said associated pair of bit lines with each other and with a source of a third potential different from said first potential and said second potential, and applying the second control signal to the second common node to equilibrate the second portion of the second portion of the sense amplifier coupled to said one pair of associated bit lines.  
   
   
   
       51 . A memory, comprising: 
 a control circuit;    a plurality of bit lines, organized into a plurality of pairs of associated bit lines;    a plurality of word lines;    a plurality of memory cells, each memory cell being coupled to one of said plurality of bit lines and one of said plurality of word lines; and    a plurality of sense amplifiers, each sense amplifier being coupled to said control circuit and to a respective pair of associated bit lines, each sense amplifier having a second portion with a first common node and a first portion with a second common node,    wherein said control circuit performs an equilibrate operation on one pair of associated bit lines by 
 at a first time, 
 applying a first control signal to the first common node to equilibrate the second portion of the sense amplifier coupled to said one pair of associated bit lines to a first potential; and  
 applying a second control signal to the second common node to equilibrate the first portion of the sense amplifier coupled to said one pair of associated bit lines to a second potential;  
 
 at a second time, different from said first time, 
 coupling said associated pair of bit lines with each other.  
 
   
   
   
       52 . The memory of  claim 51 , wherein said first potential and said second potential are chosen from a group consisting of a ground potential and a DC power supply voltage.  
   
   
       53 . The memory of  claim 51 , wherein said first potential and said second potential are chosen from a group consisting of a ground potential and a half DC power supply voltage.  
   
   
       54 . A method for equilibrating a first bit line and a second bit line coupled to a sense amplifier, comprising: 
 at a first time, 
 equilibrating the first bit line to a first potential using a second portion of the sense amplifier; and  
 equilibrating the second bit line to a second potential using a first portion of the sense amplifier; and  
   at a second time, different from the first time, 
 coupling said first bit line with said second bit line.  
   
   
   
       55 . The method of  claim 54 , wherein said first potential and said second potential are chosen from a group consisting of a ground potential and a DC power supply voltage.  
   
   
       56 . The method of  claim 54 , wherein said first potential and said second potential are chosen from a group consisting of a ground potential and a half DC power supply voltage.