Error detector, semiconductor device, and error detection method

Abstract

An error detector at a receiver comprises a feedback shift register. A shift direction in the feedback shift register is opposite to a shift direction at a transmitter in generating a transmission bit string by using a specified generator polynomial. A reception bit string is inputted to the feedback shift register in reverse order to the transmission bit string was generated at the transmitter so that errors in the reception bit string is detected by obtaining the remainder. Another error detector at a receiver comprises first and second feedback shift registers. Respective shift directions in the first and second feedback shift registers are the same as and opposite to a shift direction at a transmitter in generating a transmission bit string. The reception bit string is inputted to the first feedback shift register in the same order in which the transmission bit string was generated, while the reception bit string is inputted to the second feedback shift register in reverse order to one which the transmission bit string was generated. Errors in the reception bit string are detected by comparing respective remainders obtained by the first and second feedback shift registers. This reduces the processing time required for the error detection and increases efficiency in detecting errors in transmitted data.

1 . An error correcting and detecting device comprising: 
 a viterbi-decoder for correcting an error of a convolutional-coded bit string, and outputting a reception bit string in an order opposite to said convolutional-coded bit string; and    an error detector for detecting an error of said reception bit string which is in a same order as outputs of said viterbi-decoder, wherein    said error detector comprises a feedback shift register and a comparing unit for detecting said error of said reception bit string based on a value of said feedback shift register and compared with an initial value of a feedback shift register of a transmitter side by said comparing unit,    said feedback shift register of the transmitter side has stages maintaining some logical values, as initial values, and    said comparing unit has a judging circuit that judges that there are no errors when values maintained at stages of the feedback shift register of a receiver side are all logical values that are the same as the initial value.    
     
     
         2 . The error correcting and detecting device according to  claim 1 , said error detector further comprising a feedback shift register whose shift direction and feedback direction are opposite to ones in generating a transmission bit stream by using a specified generator polynomial of said transmitter side.  
     
     
         3 . An error correcting and detecting device for correcting an error of a convolutional-coded bit string and for detecting an error of the error-corrected bit string, said error detecting and correcting device comprising: 
 a viterbi-decoder for correcting an error of said convolutional-coded bit string, and outputting a reception bit string in an order opposite to said convolutional-coded bit string; and    an error detector for detecting an error of said reception bit string which is in a same order as outputs of said viterbi-decoder, wherein    said error detector comprises a feedback shift register and a comparing unit for detecting said error of said reception bit string based on a value of said feedback shift register and compared with an initial value of a feedback shift register of a transmitter side by said comparing unit,    said feedback shift register of the transmitter side has stages maintaining some logical values, as initial values, and    said comparing unit has a judging circuit that judges that there are no errors when values maintained at stages of the feedback shift register of a receiver side are all logical values that are the same as the initial value.    
     
     
         4 . The error correcting and detecting device according to  claim 3 , said error detector further comprising a feedback shift register for dividing said reception bit string by a generator polynomial.  
     
     
         5 . The error correcting and detecting device according to  claim 4 , wherein the shift direction and the feedback direction in said feedback shift register are opposite to ones in generating a transmission bit stream by using a specified generator polynomial of said transmitter side.  
     
     
         6 . A receiving unit comprising: 
 a receiver for receiving a convolutional-coded bit string;    a viterbi-decoder for correcting an error of a convolutional-coded bit string and outputting a reception bit string in an order opposite to said convolutional-coded bit string; and    an error detector for detecting an error of said reception bit string which is in a same order as outputs of said viterbi-decoder, wherein    said error detector comprises a feedback shift register and a comparing unit for detecting said error of said reception bit string based on a value of said feedback shift register and compared with an initial value of a feedback shift register of a transmitter side by said comparing unit,    said feedback shift register of the transmitter side has stages maintaining some logical values, as initial values, and    said comparing unit has a judging circuit that judges that there are no errors when values maintained at stages of the feedback shift register of a receiver side are all logical values that are the same as the initial value.    
     
     
         7 . The receiving unit according to  claim 6 , said error detector further comprising a feedback shift register whose shift direction and feedback direction are opposite to ones in generating a transmission bit stream by using a specified generator polynomial of said transmitter side.  
     
     
         8 . A receiving unit for correcting an error of a convolutional-coded bit string and for detecting an error of the error-corrected bit string, said receiving unit comprising: 
 a viterbi-decoder for correcting an error of said convolutional-coded bit string and outputting a reception bit string in an order opposite to said convolutional-coded bit string; and    an error detector for detecting an error of said reception bit string which is in a same order as outputs of said viterbi-decoder, wherein    said error detector comprises a feedback shift register and a comparing unit for detecting said error of said reception bit string based on a value of said feedback shift register and compared with an initial value of a feedback shift register of a transmitter side by said comparing unit,    said feedback shift register of the transmitter side has stages maintaining some logical values, as initial values, and    said comparing unit has a judging circuit that judges that there are no errors when values maintained at stages of the feedback shift register of a receiver side are all logical values that are the same as the initial value.    
     
     
         9 . The receiving unit according to  claim 8 , wherein said error detector further comprises a feedback shift register.  
     
     
         10 . The receiving unit according to  claim 9 , wherein the shift direction and the feedback direction in said feedback shift register are opposite to ones in generating a transmission bit stream by using a specified generator polynomial of said transmitter side.