Method and apparatus for generating a second signal having a clock based on a second clock from a first signal having a first clock

Abstract

An apparatus for generating a second signal having a clock based on a second clock from a first signal with a first clock comprises first and second means for sampling the first signal to determine whether the first signal has a predetermined logic state, wherein first means samples the first signal with the second clock, and second means samples the first signal with a clock phase shifted to the second clock. Means for generating the second signal generates the second signal based on the second clock if it has been determined by at least one means for sampling that the first signal has the predetermined state. Especially for time critical applications, such as a DDR-RAM, a valuable latency saving is provided by the present invention.

1 . A method for generating a second signal having a clock based on a second clock from a first signal having a first clock, comprising: 
 sampling the first signal with the second clock to determine whether the first signal has a predetermined logic state;    sampling the first signal with a clock phase shifted to the second clock to determine whether the first signal has the predetermined logic state; and    if at least one of the sampling steps has determined that the first signal has the predetermined logic state, generating the second signal based on the second clock beginning with the subsequent clock cycle of the second clock.    
   
   
       2 . An apparatus for generating a second signal having a clock based on a second clock from a first signal having a first clock, comprising: 
 means for sampling the first signal with the second clock to determine whether the first signal has a predetermined logic state;    means for sampling the first signal with a clock phase shifted to the second clock to determine whether the first signal has the predetermined logic state; and    means for generating the second signal based on the second clock beginning with the subsequent clock cycle of the second clock if it has been determined by at least one of the sampling means that the first signal has the predetermined logic state.    
   
   
       3 . The apparatus according to  claim 2 , wherein the first and second signals are asynchronous control signals.  
   
   
       4 . The apparatus according to  claim 2 , wherein the samplings are carried out by the sampling means at the rising or falling edge of the second clock or the clock phase shifted to the second clock.  
   
   
       5 . The apparatus according to  claim 2 , wherein the clock phase shifted to the second clock is phase shifted by 180° from the second clock.  
   
   
       6 . The apparatus according to  claim 2 , wherein 
 the means for sampling the first signal with the second clock includes; 
 a first clock state controlled flip-flop driven by the second clock with an input where the first signal is applied and an output for outputting a first sampling signal indicating a logic state of the first signal sampled with the second clock, and  
   the means for sampling the first signal with a clock phase shifted to the second clock includes; 
 a second clock state controlled flip-flop driven by the clock phase shifted to the second clock with an input where the first signal is applied and an output for outputting a second sampling signal indicating a logic state of the first signal sampled with the clock phase shifted to the second clock.  
   
   
   
       7 . The apparatus according to  claim 6  wherein, the first and the second clock state controlled flip-flops are constructed the same way.  
   
   
       8 . The apparatus according to claims  6 , further comprising: 
 means for carrying out an OR link having a first input connected to the output of the first clock state controlled flip-flop, a second input connected to the output of the second clock state controlled flip-flop and an output connected to means for generating, wherein means for generating is responsive to means for carrying out an OR link to begin generating the second signal at the subsequent clock cycle.    
   
   
       9 . The apparatus according to one of the claims  2 , wherein means for generating comprises: 
 a clock divider for dividing the second clock by an integer multiple to obtain the second signal, wherein the clock divider is adapted to begin dividing the second clock at the same time the subsequent clock cycle of the second clock occurs such that the second signal has clock pulses the first one of which occurs at the time the subsequent clock cycle of the second clock occurs, and the following clock pulses of which occur every integer multiple of said integer multiple of a clock cycle period of the second clock from that time, wherein the portions of the second signal between the clock pulses in which no clock pulses occur are said integer multiple of the clock cycle period of the second clock long.    
   
   
       10 . The method according to  claim 1 , wherein the step of generating comprises switching a reset signal applied to a second-signal generating circuit being clocked by the second clock responsive to at least one of the sampling steps determining that the first signal has the predetermined logic state, the second-signal generating circuit being adapted to start generating the second signal after switching the reset signal at the subsequent clock cycle such that the second signal has clock pulses the first one of which occurs at the time the subsequent clock cycle of the second clock occurs.  
   
   
       11 . The apparatus according to  claim 2 , wherein the means of generating comprises a second-signal generating circuit being clocked by the second clock and means for switching a reset signal applied to the second-signal generating circuit responsive to at least one of the sampling means determining that the first signal has the predetermined logic state, the second-signal generating circuit being adapted to start generating the second signal after switching the reset signal at the subsequent clock cycle such that the second signal has clock pulses the first one of which occurs at the time the subsequent clock cycle of the second clock occurs.  
   
   
       12 . The apparatus according to  claim 12 , wherein the second-signal generating circuit comprises a flip-flop clocked by the second clock.  
   
   
       13 . The apparatus according to  claim 2 , wherein the means for generating the second signal is designed such that the generation of the second signal is performed such that the generation begins at a clock cycle of the second clock beginning with a clock pulse of the second clock which immediately follows the time when it has been determined by at least one of the sampling means that the first signal has the predetermined logic state.  
   
   
       14 . The apparatus according to  claim 2 , wherein the means for sampling the first signal with the second clock, the means for sampling the first signal with a clock phase shifted to the second clock, and the means for generating the second signal are designed such that the predetermined logic state is a logic high value.