Use of analog-valued floating-gate transistors to match the electrical characteristics of interleaved and pipelined circuits

Abstract

Methods of and apparatuses for matching the signal delay, clock timing, frequency response, gain, offset, and/or transfer function of signal pathways in electrical circuits such as, for example, time-interleaved and pipelined circuits using analog-valued floating-gate MOSFETs are disclosed. The methods and apparatuses disclosed are applicable to a variety of circuits, including but not limited to, sample-and-hold or track-and-hold circuits, quadrature mixers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), analog or digital filters, and amplifiers.

1 . A signal processing apparatus, comprising: 
 an electrical circuit; and    a floating-gate field effect transistor disposed in a first circuit pathway of the circuit,    wherein an amount of charge present on the floating gate of the floating-gate transistor is used to match a first circuit characteristic in the first circuit pathway to a second circuit characteristic in a second circuit pathway of the circuit.    
   
   
       2 . The signal processing apparatus of  claim 1  wherein the first and second circuit characteristics correspond to relative delays presented to signals transmitted in the first and second circuit pathways.  
   
   
       3 . The signal processing apparatus of  claim 1  wherein the first and second circuit characteristics correspond to relative gains of circuit elements in the first and second circuit pathways.  
   
   
       4 . The signal processing apparatus of  claim 1  wherein the first and second circuit characteristics relate to clock timing, frequency response, offset or transfer functions of the first and second circuit pathways.  
   
   
       5 . The signal processing apparatus of  claim 1  wherein the circuit comprises a pipelined circuit.  
   
   
       6 . The signal processing apparatus of  claim 1  wherein the circuit comprises a time-interleaved circuit.  
   
   
       7 . The signal processing apparatus of  claim 1  wherein the circuit comprises an analog-to-digital converter.  
   
   
       8 . The signal processing apparatus of  claim 2  wherein the circuit comprises an analog-to-digital converter.  
   
   
       9 . The signal processing apparatus of  claim 3  wherein the circuit comprises an analog-to-digital converter.  
   
   
       10 . The signal processing apparatus of  claim 1  wherein the circuit comprises a digital-to-analog converter.  
   
   
       11 . The signal processing apparatus of  claim 3  wherein the circuit comprises a digital-to-analog converter.  
   
   
       12 . The signal processing apparatus of  claim 1  wherein the charge stored on the floating gate can be modified during operation of the circuit.  
   
   
       13 . A signal processing apparatus, comprising: 
 means for receiving an input signal at an input node of a circuit;    means for splitting the input signal into first and second circuit paths of said circuit;    a floating-gate field effect transistor disposed in the first circuit path; and    means for modifying a first circuit characteristic in the first circuit path relative to a second circuit characteristic in the second circuit path by adjusting an amount of charge stored on a floating of the floating-gate field effect transistor.    
   
   
       14 . The signal processing apparatus of  claim 13  wherein the first circuit characteristic comprises a delay presented to a signal transmitted in the first circuit path.