Semiconductor device having low parasitic resistance and small junction leakage characteristic

Abstract

A semiconductor device includes diffusion layers formed in a SOI layer under a side-wall, a channel formed between the diffusion layers, silicide layers sandwiching the diffusion layers wherein interface junctions between the diffusion layers and the silicide layers are (111) silicon planes.

1 - 4 . (canceled)  
     
     
         5 . A semiconductor device, comprising; 
 a silicon substrate having a top surface and a bottom surface;    an insulator formed on the entire top surface;    a silicon layer formed on the insulator, which acts as a channel region;    silicon diffusion layers sandwiching the channel region; and    silicide layers formed on the insulator by reacting silicon and metal, sandwiching the silicon diffusion layers, each silicide layer forming an interface junction with one of the diffusion layers;    wherein each interface junction includes a (111) silicon plane.    
     
     
         6 . A semiconductor device as claimed in  claim 5 , wherein the silicide layer is contacting the insulator.  
     
     
         7 . A semiconductor device as claimed in  claim 5 , wherein each silicide layer is metal silicide and has a crystallographic structure that is a cubic system.  
     
     
         8 . A semiconductor device as claimed in  claim 7 , wherein each interface junction further includes a (111) metal silicide plane.  
     
     
         9 . A method of manufacturing a semiconductor device, comprising: 
 preparing a silicon substrate having source and drain regions sandwiching a channel region;    forming a metal layer on the source and drain regions;    forming first silicide layers in a first stable phase in an area of the source and drain regions by performing a first thermal treatment on the silicon substrate;    forming amorphous silicon layers in another area of the source and drain regions; and    phase-transferring the first silicide layers to second silicide layers in a second stable phase, and expanding each second silicide layer in one of the amorphous silicon layers by performing on the silicon substrate a second thermal treatment at a temperature higher than a temperature of the first thermal treatment;    wherein the second thermal treatment forms interface junctions, each including a (111) silicon plane between the silicon substrate and one of the second silicide layers.    
     
     
         10 . A method of manufacturing a semiconductor device as claimed in  claim 9 , the amorphous silicon layers are formed by an ion implantation method.  
     
     
         11 . A method of manufacturing a semiconductor device as claimed in  claim 9 , each second silicide layer includes di-silicide, and a concentration of metal contained in the first silicide layer is higher than that contained in the second silicide layer.  
     
     
         12 . A method of manufacturing a semiconductor device as claimed in  claim 9 , the second thermal treatment forms the interface junctions, each further including a (111) metal silicide plane.  
     
     
         13 . A method of manufacturing a semiconductor device, comprising: 
 preparing a silicon substrate;    forming an insulator on the silicon substrate;    forming a silicon layer having diffusion layers and a channel region between the diffusion layers on the insulator;    forming a metal layer on the diffusion layers;    forming a first silicide layer in a first stable phase in an area of each diffusion layer by performing a first thermal treatment on the silicon substrate; and    phase-transforming the first silicide layer to a second silicide layer in a second stable phase, and expanding each second silicide layer in another area of one of the diffusion layers by performing on the silicon substrate a second thermal treatment at a temperature higher than a temperature of the first thermal treatment, wherein each second silicide layer reaches the insulator and the diffusion layers adjacent to the channel region remains;    wherein the second thermal treatment forms interface junctions, each including a (111) silicon plane between one of the remaining diffusion layer and one of the second silicide layer.    
     
     
         14 . A method of manufacturing a semiconductor device as claimed in  claim 13 , each second silicide layer includes di-silicide, and a concentration of metal contained in the first silicide is higher than that contained in the second silicide.  
     
     
         15 . A method of manufacturing a semiconductor device as claimed in  claim 13 , the second thermal treatment forms the interface junctions, each further including a (111) metal silicide plane.  
     
     
         16 . A method of manufacturing a semiconductor device, comprising: 
 preparing the silicon substrate having source and drain regions sandwiching a channel region;    forming a metal layer on the source and drain regions;    forming first silicide layers in a first stable phase in an area of the source and drain regions by performing a first thermal treatment on the silicon substrate;    forming amorphous silicon layers in another area of the source and drain regions;    phase-transferring the first silicide layers to second silicide layers in a second phase, and expanding each second silicide layer in one of the amorphous silicon layers by performing a second thermal treatment on the silicon substrate until a bottom of each second silicide layer reaches the silicon substrate; and    phase-transferring each second silicide layer to a third silicide layer in a third stable phase, and expanding each third silicide layer in one of the amorphous silicon layers toward the channel region by performing a third thermal treatment on the silicon substrate until an edge of each third silicide layer reaches the channel region of the silicon substrate, wherein temperatures of the second and third thermal treatments are higher than a temperature of the first thermal treatment;    wherein the third thermal treatment forms interface junctions, each including a (111) silicon plane between the silicon substrate and one of the third silicide layer.    
     
     
         17 . A method of manufacturing a semiconductor device as claimed in  claim 16 , the amorphous silicon layers are formed by an ion implantation method.  
     
     
         18 . A method of manufacturing a semiconductor device as claimed in  claim 16 , each third silicide layer includes di-silicide, and a concentration of metal contained in the first or second silicide layer is higher than that contained in the third silicide layer.  
     
     
         19 . A method of manufacturing a semiconductor device as claimed in  claim 16 , a concentration of metal contained in the first silicide layer is higher than that contained in the second silicide layer.  
     
     
         20 . A method of manufacturing a semiconductor device as claimed in  claim 16 , the third thermal treatment forms the interface junctions, each further including a (111) metal silicide plane.  
     
     
         21 . A method of manufacturing a semiconductor device, comprising: 
 preparing a silicon substrate;    forming an insulator on the silicon substrate;    forming a silicon layer having diffusion layers and a channel region between the diffusion layers on the insulator;    forming a metal layer on the diffusion layers;    forming a first silicide layer in a first stable phase in an area of each diffusion layer by performing a first thermal treatment on the silicon substrate;    phase-transforming the first silicide layer to a second silicide layer in a second stable phase, and expanding each second silicide layer in another area of one of the diffusion layers by performing a second thermal treatment on the silicon substrate until a bottom of each second silicide layers reaches the insulator; and    phase-transferring the second silicide layer to a third silicide layer in a third stable phase, and expanding each third silicide layer in other areas in one of the diffusion layer toward the channel region by performing a third thermal treatment on the silicon substrate while the diffusion layers adjacent to the channel region remains, wherein temperatures of the second or third thermal treatment are higher than a temperature of the first thermal treatment;    wherein the third thermal treatment forms interface junctions, each including a (111) silicon plane between one of the remaining diffusion layers and one of the second silicide layers.    
     
     
         22 . A method of manufacturing a semiconductor device as claimed in  claim 21 , each third silicide layer includes di-silicide, and a concentration of metal contained in the first or second silicide layer is high than that contained in the third silicide layer.  
     
     
         23 . A method of manufacturing a semiconductor device as claimed in  claim 21 , a concentration of metal contained in the first silicide layer is higher than that contained in the second silicide layer.  
     
     
         24 . A method of manufacturing a semiconductor device as claimed in  claim 21 , the third thermal treatment forms the interface junctions, each further including a (111) metal silicide plane.  
     
     
         25 . A semiconductor device comprising: 
 a silicon substrate having an insulating layer;    a silicon layer formed on the insulating layer, the silicon layer including a pair of diffusion portions and a channel portion located between the diffusion portions;    a gate insulating layer formed on the channel portion;    a gate electrode formed on the gate insulating layer;    a pair of side walls formed on the diffusion portions and the gate electrode; and    a pair of silicide layers formed on the insulating layer and on the diffusion portions, respectively, so that a pair of interface junctions are formed at interfaces between the silicide layers and the diffusion portions;    wherein each of the interface junctions includes a (111) silicon plane.    
     
     
         26 . A semiconductor device as claimed in  claim 25 , wherein each of the interface junctions further includes a (111) metal silicide plane.  
     
     
         27 . A semiconductor device as claimed in  claim 25 , wherein the interface junctions are located under the side walls.  
     
     
         28 . A semiconductor device as claimed in  claim 25 , wherein the diffusion layers and the silicide layers act as a source and a drain.  
     
     
         29 . A semiconductor device as claimed in  claim 25 , wherein each of the interfaces has a single interface plane.  
     
     
         30 . A semiconductor device as claimed in  claim 25 , wherein each of the interfaces has a plurality of interface planes that are formed in parallel.  
     
     
         31 . A semiconductor device, comprising: 
 a silicon substrate;    an insulator, which is formed on the silicon substrate;    an SOI layer, which is formed on the insulator, wherein the SOI has an intervening area, a first diffusion area next to the intervening area, a first silicide area next to the first diffusion area, a second diffusion area next to the intervening area, a second silicide area next to the second diffusion area, and wherein each interface between the diffusion area and the silicide area is a (111) silicon plane;    a gate electrode, which is formed on the SOI layer in the intervening area; and    sidewalls, which are formed on side surfaces of the gate electrode    
     
     
         32 . The semiconductor device according to  claim 30 , wherein each (111) silicon plane expands towards the insulator.  
     
     
         33 . The semiconductor device according to  claim 30 , wherein each silicide area is a metal silicide area.  
     
     
         34 . The semiconductor device according to  claim 33 , wherein each metal silicide area is formed of CoSi 2 .  
     
     
         35 . The semiconductor device according to  claim 30 , wherein each sidewall is formed on the SIO layer in the first and second diffusion areas.  
     
     
         36 . The semiconductor device according to  claim 30 , wherein the SOI layer has a thickness of 32 nm.