Metal wiring pattern for memory devices

Abstract

A memory integrated circuit having three layers of metallic traces disposed over a substrate assembly including various active devices. The traces are arranged to include I/O traces that are continuous in the third layer across spans of 4 or 8 memory blocks of an array, and that are interspersed on the third layer with non-I/O lines adapted to reduce interference between I/O lines. Column select lines, orthogonal to I/O lines and disposed in the third layer of metallic traces, except in the vicinity of I/O lines, are provided in a linear configuration and shielded from parallel digit lines in the first layer of traces by traces of the intervening second layer of traces. Global bleeder lines disposed in the third layer of traces are adapted to apply a standby voltage to a plurality of sense amplifiers. Other features of the invention include two layer power and ground bus traces, and row decoder and phase driver circuits disposed in throat and gap cell regions respectively.

1 - 36 . (canceled)  
   
   
       37 . A method of forming an integrated circuit memory device comprising: 
 forming a first layer of metallic traces over a substrate assembly which contains a plurality of sense amplifier portions;    forming a second layer of metallic traces over and insulated from said first layer of traces;    said second layer of traces including a first plurality of column select trace portions positioned over said sense amplifier portions;    forming a third layer of metallic traces over and insulated from said second layer of traces;    said third layer of traces including a plurality of I/O traces disposed above and substantially orthogonal to said column select traced portions; and    forming a further plurality of column select trace portions, which are substantially orthogonal to said I/O traces.    
   
   
       38 . A method of forming an integrated circuit memory device, said method comprising: 
 forming first and second adjacent wordline driver circuits, each containing respective transistors;    forming said transistors within a common active region such that both share a doped region;    forming a phase line; and    operatively connecting said phase line to said doped region.    
   
   
       39 . A method of forming an integrated circuit memory device comprising: 
 forming first, second, and third layers of metallic traces disposed above a substrate in spaced proximal, intermediate, and distal relation thereto respectively;    said first layer of traces including a plurality of digit lines;    said third layer of traces including a plurality of column select lines,    said column select lines being disposed substantially parallel to said digit lines; and    said second layer of traces including a further plurality of traces disposed between said digit lines and said column select lines and substantially orthogonal to both said digit lines and said column select lines.    
   
   
       40 . A method of forming an integrated circuit memory device comprising: 
 providing a substrate assembly;    providing a layer of metal traces disposed in substantially parallel spaced relation above said substrate assembly, said layer including a local phase trace;    providing an active region within said substrate assembly;    disposing first and second transistor gate assemblies in spaced relation above said active region, thereby defining first and second transistors; and    operatively connecting said local phase trace to said active region between said first and second gate assemblies, thereby operatively connecting said local phase trace to both said first and second transistors.    
   
   
       41 . A method as in  claim 40  further comprising: 
 providing a plurality of additional layers of metal traces; said plurality of layers disposed between said local phase trace and said substrate assembly.    
   
   
       42 . (canceled)  
   
   
       43 . A method of connecting a wordline in a memory integrated circuit comprising: 
 providing a substrate assembly including first and second memory arrays disposed in spaced relation to one another and defining a throat region therebetween;    providing within said throat region a row decoder circuit having a plurality of inputs and an output;    providing a plurality of address traces;    operatively connecting said plurality of address traces to said plurality of row decoder circuit inputs respectively;    providing first and second wordline driver circuits, each having an input and an output, within said first and second memory arrays respectively;    operatively connecting said output of said row decoder to said inputs of said first wordline driver circuit and to said input of said second wordline driver circuit; and    providing, within said first and second arrays respectively, first and second wordlines operatively connected to said respective outputs of said first and second wordline drivers.    
   
   
       44 . (canceled)