Latch-based pulse generator

Abstract

There is provided a pulse generator capable of generating a pulse with a reduced number of transistors that toggle in response to a clock signal, thereby reducing power consumption. The pulse generator includes a plurality of unit cells, wherein an n th unit cell (n is a natural number more than 2) generates a pulse in response to a divided-by-N clock signal (N is a natural number), a signal output from an (n−1) th unit cell and a signal output from an (n+1) th unit cell. The n th unit cell is reset or generates the pulse whose width is equivalent to the width of the clock signal, according to the logic level of the signal output from the n+1 th unit cell.

1 . A pulse generator comprising: 
 a first NAND gate that NANDs a first input signal and a second input signal;    a first inverter that inverts a signal output from the first NAND gate;    a second NAND gate that NANDs a divided-by-N clock signal and a signal output from the first inverter;    a second inverter that inverts a signal output from the second NAND gate; and    a latch that latches a reset signal and the signal output from the second NAND gate.    
     
     
         2 . The pulse generator of  claim 1 , wherein the second inverter generates a pulse corresponding to the divided-by-N clock signal in response to the second input signal.  
     
     
         3 . The pulse generator of  claim 1 , wherein phases of the first and second input signals are changed with a time difference.  
     
     
         4 . A pulse generator comprising: 
 a first NAND gate that NANDs a first input signal and a second input signal input to a second input terminal;    a first inverter that inverts a signal output from the first NAND gate;    a second NAND gate that NANDs a divided-by-N clock signal input to a first input terminal and a signal output from the first inverter;    a second inverter;    a first transmission circuit that responds to a signal output from the second NAND gate and a signal output from the second inverter;    a second transmission circuit that responds to the signal output from the second NAND gate and the signal output from the second inverter;    a third NAND gate that NANDs a reset signal and a signal output from the shared node and outputs the result of NAND to a third output terminal; and    a third inverter.    
     
     
         5 . The pulse generator of  claim 4 , wherein the second inverter generates a pulse whose width is equivalent to the width of the divided-by-N clock signal in response to the second input signal.  
     
     
         6 . The pulse generator of  claim 4 , wherein phases of the first and second input signals are changed with a time difference.