Semiconductor device and fabricating method thereof

Abstract

A semiconductor device and fabricating method thereof in which a lightly doped drain junction is graded using a diffusion property of dopant implanted in heavily doped source/drain region are disclosed. An example semiconductor device includes a gate electrode having a gate insulating layer underneath and disposed on a semiconductor substrate; a pair of lightly doped regions separated from each other in the semiconductor substrate and aligned with the gate electrode; a pair of heavily doped regions separated from each other in the semiconductor substrate and partially overlapped with the pair of the lightly doped regions, respectively; and a pair of diffusion source/drain regions enclosing the pair of the lightly doped regions therein.

1 . A semiconductor device comprising: 
 a gate electrode having a gate insulating layer underneath and disposed on a semiconductor substrate;    a pair of lightly doped regions separated from each other in the semiconductor substrate and aligned with the gate electrode;    a pair of heavily doped regions separated from each other in the semiconductor substrate and partially overlapped with the pair of the lightly doped regions, respectively; and    a pair of diffusion source/drain regions enclosing the pair of the lightly doped regions therein.    
   
   
       2 . The semiconductor device of  claim 1 , wherein the pair of the diffusion source/drain regions are heavily doped with additional dopant.  
   
   
       3 . The semiconductor device of  claim 2 , wherein the additional dopant is phosphor (P).  
   
   
       4 . The semiconductor device of  claim 2 , wherein junction profiles of the lightly doped regions are graded due to lateral diffusion of the additional dopant.