Method and system for a secure high bandwidth bus in a transceiver device

Abstract

A transceiver system for receiving content contained in a secure digital broadcast signal including a first component for generating a data stream from a received digital broadcast signal coupled to a first encryption/decryption unit configured to encrypt the data stream generated from the digital broadcast signal. Transceiver system includes a second component for generating a video signal to view the content contained in digital broadcast signal, coupled to a second encryption/decryption unit for decrypting the encrypted data stream received from the first component. A bus is coupled to the first and the second encryption/decryption unit. A third component is coupled to the bus for arbitration of the bus to coordinate the transmission of the encrypted data stream such that the data stream is securely transferred from the first to the second component without exposing an unencrypted data stream, maintaining the security of the content of the digital broadcast signal.

1 - 44 . (canceled)  
   
   
       45 . A transceiver system for receiving content contained in a secure digital broadcast signal, comprising: 
 a first component for generating a data stream;    a first encryption/decryption unit coupled to the first component, and for encrypting the data stream for transmission to generate an encrypted data stream;    a second component for generating a video signal for a display device;    a second encryption/decryption unit coupled to the second component and for decrypting the encrypted data stream received from the first component;    a bidirectional digital bus coupled to the first encryption/decryption unit and the second encryption/decryption unit; and    a third component coupled to the bus for controlling arbitration such that content from the data stream is securely transferred across the bus between the first encryption/decryption unit and the second encryption/decryption unit without exposing an unencrypted data stream.    
   
   
       46 . The system of  claim 45  wherein the transceiver is a set-top box.  
   
   
       47 . The system of  claim 45  wherein the first component is an audio video decode block for decoding the data stream from a digital broadcast signal.  
   
   
       48 . The system of  claim 45  wherein the second component is a graphics block for generating the video signal from the data stream received from the first component.  
   
   
       49 . The system of  claim 45  wherein the third component is a CPU (central processing unit) block coupled to the bus for managing an encryption process of the first encryption unit and the second encryption unit.  
   
   
       50 . The system of  claim 49  wherein the encryption process is key-based encryption process and the CPU block manages the distribution of keys to the first encryption unit and the second encryption unit.  
   
   
       51 . The system of  claim 49  further comprising an arbiter coupled to the CPU block for arbitration of the bus.  
   
   
       52 . The system of  claim 45  wherein the first component, second component, and third component include respective identification registers for identifying each component.  
   
   
       53 . The system of  claim 45  wherein said data stream is encrypted using an encryption process substantially compliant with DES ECB (Data Encryption Standard Electronic Code Book).  
   
   
       54 . The system of  claim 45  wherein the bus is a PCI (Peripheral Component Interconnect) compliant bus and each encryption unit performs encryption and decryption.  
   
   
       55 . The system of  claim 45  further comprising a front end block coupled to the bus for receiving the digital broadcast signal and generating the data stream therefrom, the first component coupled to receive the data stream from the front end block via the bus.  
   
   
       56 . The system of  claim 45  wherein the data stream is substantially compliant with a version of the MPEG (Moving Pictures Experts Group) format.  
   
   
       57 . In a set-top box transceiver, a high security bus architecture for implementing secure transmission of data between components of the transceiver, comprising: 
 a bus;    a first encryption/decryption unit coupled to the bus for encrypting a data stream to generate an encrypted data stream, the data stream received from a first component;    a second encryption/decryption unit coupled to the bus for decrypting the encrypted data stream received from the first encryption/decryption unit via the bus, the data stream for transmission to a second component; and    a third component coupled to the bus for controlling arbitration of the bus to coordinate transmission of the encrypted data stream from the first encryption/decryption unit to the second encryption/decryption unit such that content from the data stream is securely transferred between the first encryption/decryption unit and the second encryption/decryption unit across the bus without exposing the unencrypted data stream.    
   
   
       58 . The architecture of  claim 57  wherein the first component and the first encryption unit are built into a first integrated circuit device and the second component and the second encryption unit are built into a second integrated circuit device.  
   
   
       59 . The architecture of  claim 57  wherein the first component is an audio video decode block for decoding the data stream from the external source.  
   
   
       60 . The architecture of  claim 57  wherein the second component is a graphics block for generating a video signal from the data stream received from the first component.  
   
   
       61 . The architecture of  claim 57  wherein the first component is a conditional access block for descrambling the digital broadcast signal.  
   
   
       62 . The architecture of  claim 57  wherein the second component is an audio video decode block for decoding the data stream received from the first component.  
   
   
       63 . The architecture of  claim 57  wherein the third component is a CPU (central processing unit) block coupled to the bus for managing an encryption process of the first encryption unit and the second encryption unit.  
   
   
       64 . The architecture of  claim 63  wherein the encryption process is key-based encryption process and the CPU block manages the distribution of keys to the first encryption unit and the second encryption unit via the bus.  
   
   
       65 . The architecture of  claim 63  further comprising an arbiter coupled to the CPU block for arbitration of the bus.  
   
   
       66 . The architecture of  claim 63  wherein the first component, second component, and third component include respective identification registers for implementing component identification via the bus.  
   
   
       67 . The architecture of  claim 63  wherein said data stream is encrypted using an encryption process substantially compliant with DES ECB (Data Encryption Standard Electronic Code Book).  
   
   
       68 . The architecture of  claim 63  wherein the bus is a PCI (Peripheral Component Interconnect) compliant bus and provides bi-directional communication between the first component and the second component.  
   
   
       69 . In a transceiver for receiving a digital broadcast signal, a method for implementing secure transmission of data from the digital broadcast signal between internal components of the transceiver via a bus, the method comprising the steps of: 
 a) accessing a digital broadcast signal using a first component of a transceiver;    b) generating a data stream by descrambling the digital broadcast signal using the first component;    c) encrypting the data stream using a first encryption/decryption unit to generate an encrypted data stream;    d) controlling arbitration of a bus to coordinate transmission of the encrypted data stream on the bus;    e) transmitting the encrypted data stream to a second component via the bus; and    f) decrypting the data stream using a second encryption/decryption unit coupled to the second component such that the bus carries only an encrypted version of the data stream without exposing the unencrypted data stream.    
   
   
       70 . The method of  claim 69  wherein the transceiver is a set-top box.  
   
   
       71 . The method of  claim 69  wherein the bus is a PCI (Peripheral Component Interconnect) compliant bus and provides bi-directional communication between the first component and the second component.  
   
   
       72 . The method of  claim 69  further comprising the step of decoding the data stream from the external source using an audio video decode block.  
   
   
       73 . The method of  claim 69  further comprising the step of generating a video signal from the data stream received from the first component using a graphics block.  
   
   
       74 . The method of  claim 69  further comprising the step of managing an encryption process of the first encryption unit and the second encryption unit using a CPU (central processing unit) block coupled to the bus.  
   
   
       75 . The method of  claim 74  wherein the encryption process is key-based encryption process and the CPU block manages the distribution of keys to the first encryption unit and the second encryption unit.  
   
   
       76 . The method of  claim 69  wherein said data stream is encrypted using an encryption routine substantially compliant with DES ECB (Data Encryption Standard Electronic Code Book).  
   
   
       77 . The method of  claim 69  wherein the data stream is substantially compliant with a version of the MPEG (Moving Pictures Experts Group) format.