US2006129708A1PendingUtilityA1

Information processing apparatus and method and recording medium

Assignee: SONY CORPPriority: Dec 17, 1999Filed: Feb 6, 2006Published: Jun 15, 2006
Est. expiryDec 17, 2019(expired)· nominal 20-yr term from priority
Inventors:Takeo Morinaga
H04N 5/781G06F 13/28H04N 9/8042H04N 5/76
50
PatentIndex Score
0
Cited by
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References
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Claims

Abstract

A control machine which uses a data amount stored in a FIFO as a trigger and allows a DMA transfer to be started according to a capacity of the FIFO allows a control machine for preparing for the DMA transfer to start to prepare a command and the like for the DMA transfer. The control machine for preparing for the DMA transfer issues the prepared command to a control machine for transferring DMA data, so that a process according to the command is started. At the time of the DMA transfer, the burden on the host CPU is reduced.

Claims

exact text as granted — not AI-modified
1 . An information processing apparatus, comprising: 
 a receiver for receiving a stream of packets of a predetermined format;    all extracting unit operable to extract packets which are recorded to a recording apparatus from the stream of packets received by the receiver;    a memory for storing the extracted packets;    a command buffer for setting address information for DMA transfer; and    an adder for adding the address information every predetermined data amount (block) of packets readout from the memory.    
   
   
       2 . An information processing apparatus according to  claim 1 , wherein the address information includes at least one of an address in the recording apparatus in which a just-previous block has been recorded, an address in the recording apparatus in which a current block is recorded, and an address in the recording apparatus in which a just-subsequent block is recorded.  
   
   
       3 . An information processing apparatus according to claim  1 , further comprising an updating unit operable to update the address information for DMA transfer.  
   
   
       4 . An information processing apparatus according to  claim 3 , wherein the updating unit has an internal counter for automatically setting the address information.  
   
   
       5 . An information processing apparatus according to  claim 4 , wherein each time the DMA transfer of one block is finished, the internal counter is counted up and address information of one block is set as the address information.  
   
   
       6 . An information processing apparatus according to  claim 3 , wherein the updating unit updates the address information for DMA transfer when the data amount of the packets stored by the memory reaches a predetermined capacity.  
   
   
       7 . An information processing apparatus according to  claim 1 , wherein the memory includes an input FIFO and an output FIFO.  
   
   
       8 . An information processing apparatus according to  claim 7 , further comprising an updating unit operable to update the address information for DMA transfer.  
   
   
       9 . An information processing apparatus according to claim  8 , wherein the updating unit updates the address information for DMA transfer when the data amount of the packets stored in the input FIFO is equal to or larger than a predetermined capacity.  
   
   
       10 . An information processing apparatus according to  claim 8 , wherein the updating unit updates the address information for DMA transfer when the data amount of the packets stored in the output FIFO is equal to or smaller than a predetermined capacity.  
   
   
       11 . An information processing apparatus according to  claim 1 , wherein the recording apparatus is a hard disk drive built in the information processing apparatus.  
   
   
       12 . A digital broadcast receiving apparatus, comprising: 
 a hard disk drive;    a receiver for receiving a stream of packets of a predetermined format;    an extracting unit operable to extract packets which are recorded into the hard disk drive from the stream of packets received by the receiver;    a memory for storing the extracted packets;    a command buffer for setting address information for DMA transfer; and    an adder for adding the address information every predetermined data amount (block) of packets read out from the memory.    
   
   
       13 . A digital broadcast receiving apparatus according to  claim 12 , wherein the address information includes at least one of an address in the hard disk drive in which a just-previous block has been recorded, an address in the hard disk drive in which a current block is recorded, and an address in the hard disk drive in which a just-subsequent block is recorded.  
   
   
       14 . A digital broadcast receiving apparatus according to  claim 12 , further comprising an updating unit operable to update the address information for DMA transfer.  
   
   
       15 . A digital broadcast receiving apparatus according to  claim 14 , wherein the updating unit has an internal counter for automatically setting the address information.  
   
   
       16 . A digital broadcast receiving apparatus according to  claim 15 , wherein each time the DMA transfer of one block is finished, the internal counter is counted up and address information of one block is set as the address information.  
   
   
       17 . A digital broadcast receiving apparatus according to  claim 14 , wherein the updating unit updates the address information for DMA transfer when the data amount of the packets stored by the memory reaches a predetermined capacity.  
   
   
       18 . A digital broadcast receiving apparatus according to  claim 12 , wherein the memory includes an input FIFO and an output FIFO.  
   
   
       19 . A digital broadcast receiving apparatus according to  claim 18 , further comprising an updating unit operable to update the address information for DMA transfer.  
   
   
       20 . A digital broadcast receiving apparatus according to  claim 19 , wherein the updating unit updates the address information for DMA transfer when the data amount of the packets stored in the input FIFO is equal to or larger than a predetermined capacity.  
   
   
       21 . A digital broadcast receiving apparatus according to  claim 19 , wherein the updating unit updates the address information for DMA transfer when the data amount of the packets stored in the output FIFO is equal to or smaller than a predetermined capacity.  
   
   
       22 . An information processing method, comprising: 
 receiving a stream of packets of a predetermined format;    extracting packets which are recorded to a recording apparatus from the received stream of packets;    storing the extracted packets in a memory;    setting address information for DMA transfer using a command buffer; and    adding the address information every predetermined data amount (block) of packets read out from the memory.    
   
   
       23 . A recording medium recorded with a computer-readable program for causing a computer to perform an information processing method, the method comprising: 
 receiving a stream of packets of a predetermined format;    extracting packets which are recorded to a recording apparatus from the received stream of packets;    storing the extracted packets in a memory;    setting address information for DMA transfer using a command buffer; and    adding the address information every predetermined data amount (block) of packets read out from the memory.

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