Semiconductor structure with partially etched gate and method of fabricating the same

Abstract

A semiconductor structure with partially etched gate and method of fabricating the same. A semiconductor structure with a single-sided or dual-sided partially etched gate comprises a gate dielectric layer, a gate conductive layer and a cap layer sequentially stacked on a substrate to form a gate structure, and a lining layer disposed on sidewalls of the gate structure, wherein the lining layer is partially etched to expose the adjacent gate structure. In addition, an inter-layer dielectric layer covers the gate structure and a contact is formed in the inter-layer dielectric layer, exposing the substrate and a portion of the gate structure therein, wherein the lining layer of the exposed portion of the gate structure is partially removed.

1 . A method of fabricating a semiconductor structure with partially etched gate, comprising the steps of: 
 providing a semiconductor substrate with at least two adjacent gate structures thereon, wherein each gate structure is composed of a gate dielectric layer, a gate conductive layer, a cap layer, sequentially stacked on the substrate, and a lining layer covered on sidewalls thereof;    sequentially forming a protective layer and a masking layer over the gate structures;    forming an opening in the masking layer and etching the protective layer thereunder to partially expose the lining layer covering one sidewall of the two adjacent gate structures;    removing the exposed lining layers;    removing the masking layer and the protective layer; and    forming a spacer overlying sidewalls of each gate structure to form a plurality of single-side partially etched gate structures.    
   
   
       2 . The method as claimed in  claim 1 , further comprising, after removing the exposed lining layers, the step of partially removing the gate conductive layer adjacent to the exposed lining layer.  
   
   
       3 . The method as claimed in  claim 1 , further comprising the steps of: 
 forming an inter-layer dielectric layer over the gate structures; and    performing photolithography and etching to form a bitline contact in the inter-layer dielectric layer and exposing the substrate and portions of the adjacent gate structures therein.    
   
   
       4 . The method as claimed in  claim 1 , wherein the gate conductive layer is composed of a polysilicon layer and a metal silicide layer.  
   
   
       5 . The method as claimed in  claim 4 , wherein material of the metal silicide layer is tungsten silicide.  
   
   
       6 . The method as claimed in  claim 1 , wherein the protective layer is an anti-reflection coating (ARC) layer.  
   
   
       7 . The method as claimed in  claim 1 , wherein material of the masking layer is photoresist (PR).  
   
   
       8 . The method as claimed in  claim 1 , wherein materials of the cap layer and the spacer are silicon nitride.  
   
   
       9 . The method as claimed in  claim 1 , wherein the lining layer is a rapid thermal oxide (RTO) layer.  
   
   
       10 . The method as claimed in  claim 4 , wherein the gate structure adjacent to the exposed lining layer is the metal silicide layer.  
   
   
       11 . The method as claimed in  claim 3 , wherein the opening is substantially relative to a position of the bitline contact.  
   
   
       12 . The method as claimed in  claim 3 , wherein the method for forming the opening and the bitline contact is nanoimprint lithography (NIL) or photolithography.  
   
   
       13 . The method as claimed in  claim 1 , wherein the reticle for forming the opening is bitline contact node reticle or bitline contact reticle.  
   
   
       14 . The method as claimed in  claim 1 , wherein removal of the exposed lining layer is achieved using diluted hydrofluoric acid (DHF) or buffer of etching (BOE) etchant.  
   
   
       15 . The method as claimed in  claim 2 , wherein partial removal of the gate conductive layer is achieved using of RCA1 etchant.  
   
   
       16 . A method of fabricating a semiconductor structure with partially etched gate, comprising the steps of: 
 providing a semiconductor substrate with at least two adjacent gate structures thereon, wherein each gate structure is composed of a gate dielectric layer, a gate conductive layer, a cap layer, sequentially stacked on the substrate, and a lining layer covered on sidewalls thereof;    forming a protective layer over the gate structures;    etching portions of the protective layer to partially expose the lining layer covering two sidewalls of each gate structure;    removing the exposed lining layers;    removing the protective layer; and    forming a spacer overlying sidewalls of each gate structures to form a plurality of dual-sided partially etched gate structure.    
   
   
       17 . The method as claimed in  claim 16 , further comprising, before removing the partially exposed lining layers, the steps of: 
 forming a masking layer over the protective layer; and    forming a plurality of masking patterns in the masking layer, respectively covering the protective layer over the gate structures.    
   
   
       18 . The method as claimed in  claim 16 , further comprising, after removing the exposed lining layers, the step of partially removing the gate conductive layer adjacent to the exposed lining layers.  
   
   
       19 . The method as claimed in  claim 16 , further comprising the steps of: 
 forming an inter-layer dielectric (ILD) layer over the gate structures; and    performing photolithography and etching to form a bitline contact in the inter-layer dielectric layer and exposing the substrate and portions of the adjacent gate structures therein.    
   
   
       20 . The method as claimed in  claim 16 , wherein the gate conductive layer is composed of a polysilicon layer and a metal silicide layer.  
   
   
       21 . The method as claimed in  claim 16 , wherein materials of the protective layer are an anti-reflection coating (ARC) and photoresist (PR).  
   
   
       22 . The method as claimed in  claim 16 , wherein the protective layer is an anti-reflection coating (ARC) layer and the masking layer is a photoresist (PR) layer.  
   
   
       23 . The method as claimed in  claim 16 , wherein materials of the cap layer and the spacer are silicon nitride.  
   
   
       24 . The method as claimed in  claim 19 , wherein the gate structure adjacent to the exposed lining layer is the metal silicide layer.  
   
   
       25 . The method as claimed in  claim 16 , wherein removal of the exposed lining layer is achieved using diluted hydrofluoric acid (DHF) or buffer of etching (BOE) etchant.  
   
   
       26 . The method as claimed in  claim 18 , wherein partially removing the gate conductive layer is achieved using RCA1 solution containing ammonium hydroxide (NH 4   0 H) and hydrogen peroxide (H 2 O 2 ).