Manufacturing method of an non-volatile memory cell

Abstract

A manufacturing method of a non-volatile memory cell is provided. The non-volatile memory at least includes a substrate, a gate, a first source/drain region, a composite dielectric layer and a second source/drain region. A trench is formed in a substrate and a gate is formed inside the trench. The first source/drain region is formed at the bottom of the trench. The composite dielectric layer is formed between the gate and the surface of the trench. The composite dielectric layer includes at least a charge-trapping layer. The second source/drain region is formed in the substrate next to the sides of the gate.

1 . A method of fabricating a non-volatile memory cell, comprising the steps of: 
 providing a substrate;    forming a trench in the substrate;    forming a first source/drain region at a bottom of the trench;    forming a composite dielectric layer in the trench, wherein the composite dielectric layer comprises at least a charge-trapping layer;    forming a gate over the composite dielectric layer within the trench; and    forming a second source/drain region in the substrate on each side of the gate.    
   
   
       2 . The method of  claim 1 , wherein the step of forming the trench in the substrate comprises: 
 forming a patterned mask layer having an opening over the substrate, wherein the opening exposes a portion of the substrate therein;    removing the exposed portion of the substrate to form the trench in the substrate; and    removing the patterned mask layer after forming the first source/drain region at a bottom of the trench but before forming the composite dielectric layer over a sidewall of the trench.    
   
   
       3 . The method of  claim 1 , wherein the step of forming the composite dielectric layer comprises: 
 forming a bottom oxide layer over the substrate covering a sidewall of the trench;    forming a charge-trapping layer over the bottom oxide layer; and    forming a cap oxide layer over the charge-trapping layer.    
   
   
       4 . The method of  claim 1 , wherein the step of forming the gate comprises: 
 forming a conductive layer over the composite dielectric layer, filling the trench;    etching the conductive layer to form the gate; and    removing a portion of the composite dielectric layer outside the gate.    
   
   
       5 . The method of  claim 1 , wherein the step of forming the trench in the substrate comprises: 
 forming a patterned mask layer having an opening over the substrate, wherein the opening exposes a portion of the substrate therein; and    removing the exposed portion of the substrate to form the trench in the substrate.    
   
   
       6 . The method of  claim 5  wherein the step for forming the gate within the trench comprises: 
 forming a conductive layer over the composite dielectric layer, wherein the conductive layer completely fills the trench and the opening;    removing a portion of the conductive layer and the composite dielectric layer outside the opening; and    removing the mask layer to form the gate.    
   
   
       7 . The method of  claim 1 , further comprising a step of forming a device isolation structure for defining an active region in the substrate before the step of forming the trench in the substrate.  
   
   
       8 . The method of  claim 1 , further comprising a step of forming a second source/drain region in the substrate on each side of the gate, wherein the step of forming the second source/drain region comprises: 
 forming a lightly doped region in the substrate;    forming spacers on the sidewalls of the gate; and    forming a heavily doped region in the substrate.