Charge-domain A/D converter employing multiple pipelines for improved precision

Abstract

A new architecture is provided in which a master A/D converter of limited precision controls the adjustment-charge steering of a set of similar slave A/D converter pipelines. This architecture relieves the layout constraints imposed by prior architectures and also reduces power consumption of the device. By spatially interleaving the slave pipelines in an array, the new architecture also improves accuracy.

1 . An apparatus comprising: 
 a master analog-to-digital converter (ADC) having an input adapted to receive an analog signal to be converted, the master ADC further having a digital output of at least one bit; and    a plurality of analog-to-digital converter pipelines (ADCPs) each of said ADCPs having an analog input adapted to receive said analog signal to be converted, an analog output and each of said ADCPs further having a digital input coupled to the digital output of said master ADC such that digital output bits from said master ADC are sequentially applied to said ADCPs.    
   
   
       2 . The apparatus of  claim 1  wherein said combiner output is a charge-domain signal comprising a pair of charges wherein a difference between said pair of charges represents the output signal.  
   
   
       3 . The apparatus of  claim 2  further comprising a common-mode reduction circuit having an input coupled to the output of said combiner, and having an output in which the common-mode charge is reduced relative to an output charge difference.  
   
   
       4 . The apparatus of  claim 3  wherein the output of said common-mode reduction circuit has substantially the same charge difference as said input of said common-mode reduction circuit, and wherein the output of said common-mode reduction circuit has a reduced common-mode charge.  
   
   
       5 . The apparatus of  claim 3  wherein the output of said common-mode reduction circuit has an amplified charge difference relative to said input of said common-mode reduction circuit, and wherein the output of said common-mode reduction circuit has a reduced relative common-mode charge.  
   
   
       6 . The apparatus of  claim 3  further comprising a second charge-domain ADC block, having an analog input coupled to the output of said common-mode reduction circuit and having a digital output of at least one bit.  
   
   
       7 . The apparatus of  claim 1  wherein the ADCP comprises: 
 a sample and hold circuit coupled to said input adapted to receive a signal to be converted, said sample and hold circuit having a first output and a second output;    a first charge-coupled device (CCD) signal channel coupled to the first output of said sample and hold circuit;    a second CCD signal channel coupled to the second output of said sample and hold circuit;    a first CCD scaling channel coupled to said first CCD signal channel; and    a second CCD scaling channel coupled to said second CCD signal channel,    wherein addition of charge from the respective first and second scaling channels to the respective first and second signal channels is controlled by said digital input.    
   
   
       8 . The apparatus of  claim 7  wherein said first CCD scaling channel and said second CCD scaling channel include respective reference charges which are substantially equal.  
   
   
       9 . The apparatus of  claim 7  wherein said first CCD signal channel, said second CCD signal channel, said first CCD scaling channel and said second CCD scaling channel include a plurality of stages.  
   
   
       10 . The apparatus of  claim 9  wherein each stage of said first CCD scaling channel and said second CCD scaling channel have a respective reference charge and wherein a value of a reference charge in a respective stage is approximately half a value of a reference charge of a previous stage.  
   
   
       11 . An apparatus comprising: 
 a master analog-to-digital converter (ADC) having an input adapted to receive an analog signal to be converted, the master ADC further having a digital output of at least one bit; and    at least three analog-to-digital converter pipelines (ADCP) each having an analog input adapted to receive said analog signal to be converted, an analog output and each of said ADCPs further having a digital input coupled to the digital output of said master ADC such that said master ADC drives each of said at least three ADCPs.    
   
   
       12 . A charge domain apparatus comprising: 
 a master analog-to-digital converter (ADC) having an input adapted to receive an analog signal to be converted, the master ADC further having a digital output of at least one bit; and    a plurality of analog-to-digital converter pipelines (ADCPs), each of said ADCPs having an input adapted to receive said analog signal to be converted, each of said ADCPs further having a digital input coupled to the digital output of said master ADC, and each of said ADCPs further having an analog output wherein said master ADC feeds each of said plurality of ADCPs; and    means for adding charge at each stage of each ADCP based upon the at least one output bit from said master ADC such that said ADCP outputs are provided having a reduced charge difference as compared to a sampling result.    
   
   
       13 . A method of converting an analog signal into digital form, the method comprising: 
 sampling the analog signal in a master (analog-to-digital converter) ADC;    sampling the analog signal in a plurality of analog-to-digital converter pipelines (ADCPs), resulting in an output comprising a charge pair having a difference proportional to a characteristic of the signal;    performing an analog-to-digital conversion in the master ADC, resulting in at least one output bit; and    selectively adding charge at each stage of each ADCP based upon the at least one output bit from the master ADC, resulting in ADCP outputs having a reduced charge difference as compared to a sampling result.    
   
   
       14 . An apparatus comprising: 
 a master analog-to-digital converter (ADC) having an input adapted to receive an analog signal to be converted, the master ADC further having a digital output of at least one bit;    a first analog-to-digital converter (ADCP) having an input adapted to receive said analog signal to be converted, and ADCP further having a digital input coupled to the digital output of said master ADC, said first ADCP further having an analog output; and    wherein the apparatus is constructed and arranged to enable said analog signal to be converted to be received simultaneously at the master ADC and first ADCP.    
   
   
       15 . The apparatus of  claim 14 , wherein said first ADCP is a first one of a plurality of ADCPs, each respective ADCP having a digital input coupled to the digital output of said master ADC and having an input adapted to receive said analog signal to be converted, the apparatus being constructed and arranged to enable said analog signal to be converted to be received simultaneously at the master ADC and at each of the respective plurality of ADCPs, and wherein the apparatus further comprises a combiner having inputs adapted to receive the analog outputs from each of the plurality of ADCPs, said combiner further having an output.  
   
   
       16 . The apparatus of  claim 15 , wherein the ADCP comprises: 
 a sample and hold circuit coupled to said input adapted to receive a signal to be converted, said sample and hold circuit having a first output and a second output;    a first charge-coupled device (CCD) signal channel coupled to the fist output of said sample and hold circuit;    a second CCD signal channel coupled to the second output of said sample and hold circuit;    a first CCD scaling channel coupled to said first CCD signal channel; and    a second CCD scaling channel coupled to said second CCD signal channel,    wherein additional of charge from the respective first and second scaling channels to the respective first and second signal channels is controlled by said digital input.