Semiconductor device and manufacturing method for semiconductor device

Abstract

A conventional power MOSFET structure is difficult to improve a breakdown voltage of an element even using a super-junction structure. A power MOSFET according to an embodiment of the invention is a semiconductor device of a super-junction structure, including: a gate electrode filled in a trench formed on a semiconductor substrate; a gate wiring metal forming a surface layer; and a gate electrode plug connecting between the gate electrode and the gate wiring metal. Thus, a polysilicon layer necessary for the conventional typical power MOSFET is unnecessary. That is, column regions of an element active portion and an outer peripheral portion can be formed under the same conditions. As a result, it is possible to improve an element breakdown voltage as compared with the conventional one.

1 . A semiconductor device having a super-junction structure, comprising: 
 a gate electrode filled in a trench formed on a semiconductor substrate;    a gate wiring metal forming a surface layer; and    a gate electrode plug connecting between the gate electrode and the gate wiring metal.    
   
   
       2 . The semiconductor device according to  claim 1 , wherein a column region of an element active portion as an active portion of an element has substantially the same depth as a column region of an outer peripheral portion as an outer periphery of the element active portion.  
   
   
       3 . The semiconductor device according to  claim 2 , further comprising: 
 an element isolation region for element isolation;    an interlayer insulating layer formed on the element isolation region; and    a polysilicon layer formed between the element isolation region and the interlayer insulating layer.    
   
   
       4 . The semiconductor device according to  claim 3 , wherein the polysilicon layer is used as a Zener diode.  
   
   
       5 . The semiconductor device according to  claim 4 , wherein the gate electrode filled in the trench formed on the semiconductor substrate is made of the same polysilicon as the polysilicon layer.  
   
   
       6 . The semiconductor device according to  claim 1 , further comprising: 
 an element isolation region for element isolation;    an interlayer insulating layer formed on the element isolation region; and    a polysilicon layer formed between the element isolation region and the interlayer insulating layer.    
   
   
       7 . The semiconductor device according to  claim 6 , wherein the polysilicon layer is used as a Zener diode.  
   
   
       8 . The semiconductor device according to  claim 7 , wherein the gate electrode filled in the trench formed on the semiconductor substrate is made of the same polysilicon as the polysilicon layer.  
   
   
       9 . A manufacturing method for a semiconductor device, comprising: 
 forming an epitaxial layer of a first conductivity type on a semiconductor substrate of the first conductivity type;    forming an element isolation region in a predetermined region on the epitaxial layer;    forming a gate electrode filled in a trench formed on the epitaxial layer;    forming a column region of a second conductivity type in the epitaxial layer;    forming a base region of a second conductivity type on the epitaxial layer;    forming a source region of the first conductivity type in a predetermined region on the base region;    forming an interlayer insulating film throughout an entire surface of the semiconductor substrate;    forming a contact hole passing through the interlayer insulating film to expose the gate electrode on a surface;    forming a gate electrode plug using a conductor filled in the contact hole; and    forming a gate wiring metal connected with the gate wiring metal on the interlayer insulating film.    
   
   
       10 . The manufacturing method for a semiconductor device according to  claim 9 , wherein a polysilicon layer is formed on the element isolation region concurrently with the formation of the gate electrode.  
   
   
       11 . The manufacturing method for a semiconductor device according to  claim 10 , wherein a portion of the gate electrode serving as an electrode extraction portion is formed with a larger width than a width of the other portion of the gate electrode.  
   
   
       12 . The manufacturing method for a semiconductor device according to  claim 9 , wherein a portion of the gate electrode serving as an electrode extraction portion is formed with a larger width than a width of the other portion of the gate electrode.