Method and apparatus for circuit completion through the use of ball bonds or other connections during the formation of a semiconductor device

Abstract

A method used to form a semiconductor device comprises providing first and second circuit portions having first and second pad portions respectively. The second circuit portion is electrically isolated from the first circuit portion. The first and second pad portions are then electrically connected, for example with a ball bond or a wire bond, to electrically couple the first and second circuit portions. In various embodiments the semiconductor device will not function until the pad portions are electrically coupled, and in other embodiments the functionality of the device may be selectively controlled by connecting selected pad portions from a plurality of pad portions. Isolating the first and second circuit portions allows electrical operations such as antifuse programming to be carried out without adversely affecting related circuits. Once electrical operations are completed, the isolated circuit portions are electrically coupled to provide a complete circuit. Various inventive embodiments and implementations are described.

1 . A method used during fabrication of a semiconductor device comprising: 
 forming a semiconductor wafer section comprising first, second, and third pads thereon which are electrically separated from each other;    forming a first circuit portion electrically coupled with the first pad;    forming a second circuit portion electrically coupled with the second pad and electrically isolated from the first circuit portion;    forming a third circuit portion electrically coupled with the third pad and electrically isolated from the first and second circuit portions;    enabling the semiconductor device to function in only one of a first operational mode and a second operational mode by selectively electrically connecting together either the first and second pads to enable the first operational mode or the second and third pads to enable the second operational mode; and    encapsulating the semiconductor wafer section such that selectively electrically connecting together either the first and second pads or the second and third pads is not possible when the semiconductor wafer section is encapsulated.    
   
   
       2 . The method of  claim 1  further comprising attaching a single ball bond to two of the pads during the selective electrical connection.  
   
   
       3 . The method of  claim 1  further comprising attaching a wire bond to two of the pads during the selective electrical connection.  
   
   
       4 . The method of  claim 1  further comprising screen printing a conductive epoxy to two of the pads during the selective electrical connection.  
   
   
       5 . The method of  claim 1  further comprising: 
 providing a transistor during the providing of the first circuit portion and providing one of a fuse and antifuse array during the providing of the second circuit portion; and    selectively electrically connecting the first pad with the second pad thereby electrically coupling the one of the fuse and antifuse array to the transistor during the selective electrical connection of the first and second pads.    
   
   
       6 . The method of  claim 1  further comprising: 
 providing a lead frame;    attaching the wafer section to the lead frame; then    encapsulating the lead frame during the encapsulation of the semiconductor wafer section.    
   
   
       7 . A method used during fabrication of a semiconductor device, comprising: 
 providing first and second conductive pad portions electrically isolated from each other;    providing a transistor electrically coupled with the first conductive pad portion;    providing one of a fuse array and an antifuse array electrically coupled with the second conductive pad portion;    electrically coupling the second pad portion to a voltage source;    with the second pad portion electrically coupled to the voltage source, programming the array; and    subsequent to programming the array, electrically coupling the first pad portion with the second pad portion.    
   
   
       8 . The method of  claim 7  further comprising electrically coupling the second pad portion to the voltage source through a probe tip during the electrical coupling of the second pad portion with the voltage source.  
   
   
       9 . The method of  claim 7  further comprising: 
 providing a CGND node during the providing of the second pad portion;    electrically coupling the CGND node to the transistor during the electrical coupling of the first pad portion with the second pad portion; and    tying the CGND node to ground through the transistor during an operational mode of the semiconductor device subsequent to programming the array.    
   
   
       10 . A method used during fabrication of a semiconductor device comprising: 
 providing a semiconductor wafer substrate assembly;    providing a bond pad comprising at least three separate sections electrically isolated from each other, wherein the three sections of the bond pad each overlie the wafer substrate assembly;    providing at least three circuit portions with one circuit portion electrically connected with only one of the bond pad portions;    electrically interconnecting the at least three bond pad sections to electrically connect the at least three circuit portions.    
   
   
       11 . The method of  claim 10  further comprising: 
 providing a lead frame; and    subsequent to electrically interconnecting the at least three bond pad sections, attaching the semiconductor wafer substrate assembly to the lead frame.    
   
   
       12 . The method of  claim 10  further comprising attaching a ball bond to the at least three bond pad sections during the interconnection of the at least three bond pad sections.  
   
   
       13 . The method of  claim 10  further comprising screen printing a conductive material to contact the at least three bond pad sections during the interconnection of the at least three bond pad sections.  
   
   
       14 . A method used during fabrication of a semiconductor device comprising: 
 providing a semiconductor wafer substrate assembly;    providing a plurality of conductive pads electrically isolated from each other;    providing a plurality of circuits wherein each circuit is electrically connected with one of the bond pads;    selecting an operational mode of the semiconductor device by selectively connecting at least two of the plurality of conductive pads to each other to selectively connect at least two of the plurality of circuits; and    packaging the semiconductor wafer substrate assembly such that selecting the operational mode of the semiconductor device cannot be performed when the semiconductor wafer substrate assembly is packaged.    
   
   
       15 . A method used during fabrication of a semiconductor device comprising: 
 providing a semiconductor wafer section;    forming first and second spaced conductive pads on the semiconductor wafer section; and    forming first and second internal power buses on the semiconductor wafer section, wherein the first power bus is electrically connected to the first conductive pad and the second power bus is electrically connected to the second conductive pad,    wherein the first and second conductive pads are adapted to be electrically coupled to each other to electrically connect the first power bus with the second power bus.    
   
   
       16 . The method of  claim 15  further comprising forming a V SS  power bus and a V SSQ  power bus during the formation of the first and second internal power buses.  
   
   
       17 . The method of  claim 15  further comprising electrically connecting the first conductive pad with the second conductive pad to electrically connect the V SS  power bus with the V SSQ  power bus.  
   
   
       18 . A method used during fabrication of a semiconductor device having a hardwired and selectable column address strobe (CAS) latency, comprising: 
 providing at least one CAS latency select line;    forming at least a first conductive pad electrically coupled with a high potential, a second conductive pad electrically coupled with the CAS latency select line, and a third conductive pad electrically coupled with a low potential; and    selecting a CAS latency by either: 
 forming a conductor to electrically connect the first pad portion with the second pad portion to select a first CAS latency; or  
 forming a conductor to electrically connect the second pad portion with the third pad portion to select a second CAS latency which is different from the first CAS latency.  
   
   
   
       19 . The method of  claim 18  further comprising forming a ball bond during the formation of the conductor which electrically connects only two of the first, second, and third conductive pads together.  
   
   
       20 . The method of  claim 18  further comprising forming a bond wire during the formation of the conductor which electrically connects only two of the first, second, and third conductive pads together.  
   
   
       21 . The method of  claim 18  further comprising encapsulating the CAS select line and the first, second, and third conductive pads subsequent to forming the conductor.  
   
   
       22 . A method used during fabrication of a semiconductor device, comprising: 
 selectively electrically connecting conductive pads located on a surface of an integrated circuit die to provide an electrically conductive path between the conductive pads, wherein the conductive path determines an operational mode of the semiconductor device; then    encapsulating the semiconductor die in a dielectric material such that the electrically conductive path is not directly accessible from outside the dielectric material.    
   
   
       23 . A method used during fabrication of a semiconductor device, comprising: 
 selecting a desired operational mode for the semiconductor device from two or more operational modes;    selectively electrically connecting two or more conductive pads located on a surface of an integrated circuit die to provide an electrically conductive path between the two or more conductive pads, wherein the conductive path enables the desired operational mode of the semiconductor device; then    packaging the integrated semiconductor die in a dielectric material such that the electrically conductive path is not directly accessible by an end user of the semiconductor device.    
   
   
       24 . A method used during fabrication of a semiconductor device, comprising: 
 forming a semiconductor die comprising: 
 a first conductive pad electrically connected to a first circuit portion;  
 a second conductive pad electrically connected to a second circuit portion;  
 a third conductive pad electrically connected to a third circuit portion,  
   wherein the first, second, and third circuit portions are incomplete circuits;    selectively electrically connecting either the first and second conductive pads to electrically connect the first and second incomplete circuit portions to provide a first complete circuit and a first device operational mode, or the second and third conductive pads to electrically connect the second and third incomplete circuit portions to provide a second complete circuit and a second device operational mode,    wherein the semiconductor device is nonfunctional during operation if two of the conductive pads are not electrically connected.    
   
   
       25 . The method of  claim 24  wherein the first, second, and third conductive pads are adjacently located to each other and the method further comprises placing a single ball bond on either the first and second pads or on the second and third pads during the selective electrical connection.