Method of forming bit line contact via

Abstract

A method of forming a bit line contact via. The method includes providing a substrate having a transistor with a gate electrode, drain region, and source region, forming a conductive layer overlying the drain region, conformally forming an insulating barrier layer overlying the substrate, blanketly forming a dielectric layer overlying the insulating barrier layer, and forming a via through the dielectric layer and insulating barrier layer, exposing the conductive layer.

1 - 20 . (canceled)  
   
   
       21 . A semiconductor device, comprising: 
 a transistor comprising a gate electrode, a first source/drain region, and a second source/drain region;    a conductive layer overlying the first source/drain region, wherein top surface of the conductive layer is lower than that of the gate electrode;    an insulating barrier layer overlying the gate electrode and the second source/drain region;    a blanket of a dielectric layer overlying the transistor, the dielectric layer comprising a via exposing the conductive layer.    
   
   
       22 . The device as claimed in  claim 21 , wherein the conductive layer is doped polycrystalline silicon.  
   
   
       23 . The device as claimed in  claim 21 , wherein the insulating barrier layer is SiN.  
   
   
       24 . The device as claimed in  claim 21 , wherein the dielectric layer comprises an oxide.  
   
   
       25 . The device as claimed in  claim 21 , wherein the dielectric layer comprises boro-phosphosilicate glass (BPSG).  
   
   
       26 . The device as claimed in  claim 22 , wherein the conductive layer is doped with an element in either group  13  (M A) or  15  (VA) of periodic table.  
   
   
       27 . The device as claimed in  claim 22 , wherein the conductive layer is doped with As.  
   
   
       28 . A semiconductor device, comprising: 
 a substrate with a plurality of transistors thereon, each transistor comprising a gate electrode, a first source/drain region, and a second source/drain region;    a first conductive layer overlying at least one of the first source/drain regions;    a second conductive layer overlying the first conductive layer, wherein top surface of the second conductive layer is lower than that of the neighboring gate electrodes;    an insulating barrier layer overlying the gate electrodes and the second source/drain regions;    a blanket of a dielectric layer overlying the substrate, the dielectric layer comprising a via exposing the second conductive layer.    
   
   
       29 . The device as claimed in  claim 28 , wherein the first conductive layer comprises a metal/metal compound.  
   
   
       30 . The device as claimed in  claim 28 , wherein the first conductive layer comprises Ti/TiSi.  
   
   
       31 . The device as claimed in  claim 28 , wherein the first conductive layer is conformally overlying the exposed drain region and its neighboring sidewalls of the gate electrodes.  
   
   
       32 . The device as claimed in  claim 31 , wherein the first conductive layer is lower than that of the neighboring gate electrodes.  
   
   
       33 . The device as claimed in  claim 31 , wherein the first conductive layer comprises a metal/metal compound.  
   
   
       34 . The device as claimed in  claim 31 , wherein the first conductive layer comprises Ti/TiSi.  
   
   
       35 . The device as claimed in  claim 28 , wherein the conductive layer is doped polycrystalline silicon.  
   
   
       36 . The device as claimed in  claim 28 , wherein the conformal insulating barrier layer is SiN.  
   
   
       37 . The device as claimed in  claim 28 , wherein the dielectric layer comprises an oxide.  
   
   
       38 . The device as claimed in  claim 28 , wherein the dielectric layer comprises boro-phosphosilicate glass (BPSG).  
   
   
       39 . The device as claimed in  claim 28 , wherein the conductive layer is doped with an element in either group 13 (IIIA) or 15 (VA) of periodic table.  
   
   
       40 . The device as claimed in  claim 28 , wherein the conductive layer is doped with As.