Twin EEPROM memory transistors with subsurface stepped floating gates

Abstract

A memory array with memory cells arranged in rows and columns with each cell having twin EEPROMs featuring subsurface stepped floating gates for electric field concentration. The twin EEPROMs employ only a single layer of poly, one portion being a floating gate of each EEPROM and another portion being word lines. The twin EEPROMs share a common subsurface electrode by having diffused control lines and a diffused bit line. The two EEPROMs are symmetric across the common electrode.

1 . A memory array having a plurality of memory cells, each cell comprising: 
 a pair of parallel word lines, each word line having a pair of first capacitors in series therewith, each first capacitor having a pair of plates;    a bit line associated with one capacitor plate of each first capacitor;    a pair of EEPROM memory transistors each having a drain, source and gate, the drain of each memory transistor connected to the one capacitor plate of each respective first capacitor, the sources of the pair of transistors mutually joined in a common electrode, and the gate of each transistor being a floating gate having a step therein for electric field concentration; and    a pair of second capacitors each having one plate associated with a control line input terminal and another plate connected to the floating gate of an EEPROM transistor.    
     
     
         2 . The memory array of  claim 1  wherein the step in each floating gate is at least partially below a silicon surface of a silicon wafer, said step having top and bottom corners.  
     
     
         3 . The memory array of  claim 1  wherein said EEPROM transistors have first portions of a single layer of poly as floating gates.  
     
     
         4 . The memory array of  claim 3  wherein said memory cells have a second portion of said single layer of poly functioning as said word lines.  
     
     
         5 . The memory array of  claim 2  wherein said bit line is diffused below the surface of said silicon wafer.  
     
     
         6 . The memory array of  claim 1  wherein said first capacitors are formed by an intersection of said word lines with said bit line.  
     
     
         7 . The memory array of  claim 1  wherein said pair of word lines, the pair of second capacitors, and the pair of EEPROM transistors are symmetrically disposed about the common electrode.