Image processing circuit

Abstract

An image processing circuit capable of carrying out high-speed processing and improving the horizontal and vertical resolutions even with its simple structure. The pixel values a to i of a total of nine pixels, three pixels in the horizontal direction along a scanning line by three pixels in the vertical direction in which the line and adjacent lines are abreast, are extracted by a pixel value extracting section. The pixel values A 1 to A 4 of four pixels Q 1 to Q 4 generated additionally around the center pixel P 5 are determined by calculation by a pixel value calculation section. These pixel values are outputted in units of one scanning line by correlating them with two scanning lines by a pixel value output section.

1 - 10 . (canceled)  
     
     
         11 . An image processing circuit for transforming the number of pixels in each of horizontal and vertical directions into substantially twice by performing an interpolation process based on pixel values of the pixels arranged regularly in the horizontal and vertical directions, characterized by comprising: 
 pixel value extracting unit for extracting the pixel values of a total of nine pixels, three pixels in the horizontal direction by three pixels in the vertical direction; and    pixel value calculating unit for calculating the pixel values of four pixels generated additionally corresponding to positions on straight lines connecting a central pixel arranged in the center of said nine pixels and four peripheral pixels arranged in the oblique directions of the central pixel and at one-quarter the distance from said central pixel to said four peripheral pixels, on the basis of the pixel values of said nine pixels output from said pixel value extracting unit.    
     
     
         12 . The image processing circuit according to  claim 11 , characterized in that said pixel value calculating unit sets the pixel values A 1 , A 2 , A 3 , A 4  of four pixels generated additionally around said central pixel such that:  
           A 1 ={Ne +( a+b+d )−( c+f+g+h+i )}/( N− 2)    A   2   ={Ne +( b+c+f )−( a+d+g+h+i )}/( N− 2)    A 3 ={Ne +( d+g+h )−( a+b+c+f+i )}/( N− 2)    A 4 ={Ne +( f+h+i )−( a+b+c+d+g )}/( N− 2)  where the pixel values of said nine pixels including said central pixel are a, b, c, d, e, f, g, h, and i in the scan order, and N is an integer of 3 or greater.    
     
     
         13 . The image processing circuit according to  claim 12 , characterized in that by having the value of N to 10, said pixel values A 1 , A 2 , A 3 , A 4  are set such that:  
           A 1={10 e +( a+b+d )−( c+f+g+h+i )}/8    A 2 ={10 e +( b+c+f )−( a+d+g+h+i )}/8    A 3={10 e +( d+g+h )−( a+b+c+f+i )}/8    A 4={10 e +( f+h+i )−( a+b+c+d+g )}/8  
     
     
         14 . The image processing circuit according to  claim 11 , characterized in that said pixel value calculating unit sets the pixel values A 1 , A 2 , A 3 , A 4  of four pixels generated additionally around said central pixel such that:  
           A 1 ={Me +( a+b+d )−( f+h+i )}/ M      A 2 ={Me +( b+c+f )−( d+g+h )}/ M      A 3 ={Me +( d+g+h )−( b+c+f )}/ M      A 4 ={Me +( f+h+i )−( a+b+d )}/ M    where the pixel values of said nine pixels including said central pixel are a, b, c, d, e, f, g, h, and i in the scan order, and M is an integer of 2 or greater.    
     
     
         15 . The image processing circuit according to  claim 14 , characterized in that by having the value of M to 8, said pixel values A 1 , A 2 , A 3 , A 4  are set such that:  
           A 1={8 e +( a+b+d )−( f+h+i )}/8    A 2={8 e +( b+c+f )−( d+g+h )}/8    A 3={8 e +( d+g+h )−( b+c+f )}/8    A 4={8 e +( f+h+i )−( a+b+d )}/8  
     
     
         16 . The image processing circuit according to  claim 11 , characterized in that said pixel value calculating unit sets the pixel values A 1 , A 2 , A 3 , A 4  of four pixels generated additionally around said central pixel such that:  
           A 1 ={Le+ 2 b+ 2 d −( c+f+g+h )}/ L      A 2 ={Le+ 2 b+ 2 f −( a+d+h+i )}/ L      A 3 ={Le+ 2 d+ 2 h −( a+b+f+i )}/ L      A 4 ={Le+ 2 f+ 2 h −( b+c+d+g )}/ L    where the pixel values of said nine pixels including said central pixel are a, b, c, d, e, f, g, h, and i in the scan order, and L is an integer of 2 or greater.    
     
     
         17 . The image processing circuit according to  claim 16 , characterized in that by having the value of L to 10, said pixel values A 1 , A 2 , A 3 , A 4  are set such that:  
           A 1={10 e+ 2 b+ 2 d −( c+f+g+h )}/10    A 2={10 e+ 2 b+ 2 f −( a+d+h+i )}/10    A 3={10 e+ 2 d+ 2 h −( a+b+f+i )}/10    A 4={10 e+ 2 f+ 2 h −( b+c+d+g )}/10