Twin EEPROM memory transistors with subsurface stepped floating gates

Abstract

A memory array with memory cells arranged in rows and columns with each cell having twin EEPROMs featuring subsurface stepped floating gates for electric field concentration. The twin EEPROMs employ only a single layer of poly, one portion being a floating gate of each EEPROM and another portion being word lines. The twin EEPROMs share a common subsurface electrode by having diffused control lines and a diffused bit line. The two EEPROMs are symmetric across the common electrode.

1 . In an EEPROM transistor in a memory array of the EEPROM type fabricated in a silicon wafer with an oxide coating on the wafer surface, with a source, drain and floating gate, the improvement comprising a step in floating gate extending at least partially below the wafer surface and a first capacitor control element with first and second capacitor plates, the first plate connected to the floating gate.  
     
     
         2 . The transistor of  claim 1  having a second capacitor connected to a source or drain electrode.  
     
     
         3 . The transistor of  claim 1  wherein said second capacitor has plates associated with a word line and a bit line of the memory array.  
     
     
         4 . The transistor of  claim 1  wherein said step has top and bottom corners.