Method of enlarging contact area of a gate electrode, semiconductor device having a surface-enlarged gate electrode, and method of manufacturing the same

Abstract

A highly integrated semiconductor device operates at a high speed due to low resistance at the gate electrode and minimal parasitic capacitance between the gate electrode and substrate. A gate pattern is formed on a substrate, and an insulating layer is formed over the substrate including over the gate pattern. The thickness of the insulating layer is reduced until the upper surface thereof beneath the level of the upper surface of the gate electrode. A conductive layer is then formed on the substrate, and is anisotropically etched to thereby form wings constituting a first spacer on upper sidewalls of the gate pattern. Then, the insulating layer is etched to leave a portion thereof beneath the wings. This remaining portion of the insulating layer constitutes a capacitance preventative layer that serves as a measure against the subsequent forming of a parasitic capacitor when source/drain electrodes are formed by implanting ions into the substrate and heat-treating the same.

1 . A semiconductor device, comprising: 
 a semiconductor substrate, and an isolation structure, said semiconductor substrate having an active region defined by the isolation structure;    a gate insulating layer disposed on the active region of said substrate;    a gate electrode having a main body disposed on said gate insulating layer as in contact therewith, and wings extending laterally from an upper portion of said body, such that the gate electrode is T- or mushroom-shaped; and    a capacitance preventative layer of insulating material disposed under said wings of said gate electrode in contact with said body of the gate electrode and said gate insulating layer, and thereby limiting the parasitic capacitance that can be generated between the substrate and the gate electrode;    a spacer disposed both sides of said gate electrode, the spacer comprising an insulating material; and    a source electrode and a drain electrode located in the active region of said substrate, the source electrode and drain electrode being spaced apart from each other with said gate electrode being disposed therebetween.    
     
     
         2 . The semiconductor device of  claim 1 , wherein said gate electrode comprises polysilicon, and said capacitance preventative layer comprises a low temperature oxide (LTO) layer.  
     
     
         3 . The semiconductor device of  claim 1 , wherein said substrate has an anti-diffusion layer disposed beneath the gate insulating layer at both sides of the gate electrode, said anti-diffusion layer comprising anti-diffusion ions.  
     
     
         4 . The semiconductor device of  claim 3 , wherein the anti-diffusion ions are selected from the group consisting of germanium (Ge), phosphor (P), silicon (Si) and indium (In) ions.  
     
     
         5 . The semiconductor device of  claim 1 , wherein said gate electrode includes a layer comprising a metal at outer surfaces of said body and wings thereof.  
     
     
         6 . The semiconductor device of  claim 5 , wherein the metal is selected from the group consisting of titanium (Ti), tungsten (W) and cobalt (Co).  
     
     
         7 . The semiconductor device of  claim 5 , wherein a layer of said metal layer is also disposed on the source and drain electrodes.